Jasper Formal Technology Newsletter Q1 2012

FORMAL TECHNOLOGY NEWSLETTER

HOW CUSTOMERS ARE USING JASPER

 

Below is a link to presentations and video recordings from our Jasper User Group Meeting on how customers are using Jasper. If you are a Jasper user, you can view them on our Formal Expert web site at http://jasper-da.com/fe/events/2011-jasper-users-group-meeting

Featured Videos
  • Introduction/CEO Message - Kathryn Kranen, Jasper
  • AE Tips and Tricks - Lawrence Loh, Jasper
  • A Glimpse into the Future - Claudionor Coehlo, Jasper
  • Design Development, Comprehension, and RTL Transfer - Norris Ip and Shaun Giebel, Jasper
  • Architectural Modeling and Validation of the ARM ACE Protocol - Ross Weber, Jasper
  • AMBA4 and Cache Coherent Interconnect - Paul Martin, ARM
  • Embedding Formal Verification into a CPU Design and Validation Project - Laurent Arditi, ARM
  • Architectural Validation of a Communication Protocol Using ActiveModel and JasperGold - Keith Schakel, Applied Micro
  • AMD Macro IP Verification Closure - Ashok Venkatachar, AMD
Featured Presentations
  • Embedding Formal Verification into a CPU Design & Validation Project
  • Architecture Validation of Communication Protocol
  • Introduction to AMBA4 and Cache Coherent Interconnect
  • Accelerating Macro IP Verification Closure
  • Architectural Modeling and Validation of the ARM ACE Protocol
  • Jasper AE Wisdom Unveiled: Tips and Tricks for Getting Additional Edge with Jasper
  • Multiple Jasper Applications on Cortex A15 Verification
  • Clock Sensitive FIFO Verification with Jasper
  • Exhaustive Latch Flow-through Verification with Jasper
  • Improving RTL Quality and Increasing Functional Coverage
  • Advanced Debugging with Jasper Including Post-Silicon Debug
  • Simulation Savings on an Interrupt Controller with Jasper
  • Intelligent Proof Kits: A Smart Alternative to VIPs
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IN THE NEWS

 

Jasper CEO Finds Formula to Help Chipmakers Flourish – San-Jose-Mercury-News http://www.mercurynews.com/business/ci_20039050

Juniper Networks Adopts Jasper Formal Technology to Mitigate Design and Verification Risk
http://www.jasper-da.com/node/387

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EVENTS


Real-World Applications
of Formal Verification Seminar

Join Jasper Design Automation for a technical seminar on how to solve critical verification challenges using state-of-the-art formal technology.

This full-day seminar will be given by technical experts for verification experts just like you. The seminar will focus on real life problems that face design and verification engineers. We will discuss a range of issues you may encounter every day.

LOCATION: GERMANY
DATE:
MARCH 19, 2012

Register at http://www.jasper-da.com/node/381


Synopsys User Group (SNUG)

Click here for more info

Santa Clara Convention Center, Santa Clara CA
March 26 - 28, 2012

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TECHNICAL ARTICLES

 

Formally Verifying Protocols – SemiWiki
http://www.semiwiki.com/forum/content/867-architectural-modeling.html

Coherency, Verification Takes Spotlight in System Design – Chip Design Magazine
http://chipdesignmag.com/display.php?articleId=5050

Using Cache Coherency to Verify the AMBA4 Protocol
http://blogs.arm.com/soc-design/649-using-cache-coherency-to-verify-the-amba4-protocol/




Review Article Be the first to review this article
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL



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