STATS ChipPAC's Scalable 3D eWLB Solutions Deliver Performance, Height and Cost Advantages Over Substrate-Based Package-on-Package Technology

SINGAPORE--06/03/2012, UNITED STATES -- (MARKET WIRE) -- Mar 06, 2012 -- STATS ChipPAC Ltd. ("STATS ChipPAC" or the "Company") (SGX-ST: STATSChP), a leading semiconductor test and advanced packaging service provider, today announced its next-generation three dimensional (3D) embedded Wafer Level Ball Grid Array (eWLB) Package-on-Package (PoP) solutions. This innovative new 3D technology provides an ultra thin package profile height below 1.0mm, a 30% height reduction over the industry standard 1.4mm total stacked package height.

Market demand for advanced, multi-functional portable electronic devices is driving the need for semiconductor packages with higher thermal and electrical performance, increased bandwidth and speed in an ultra thin package profile. PoP has been a successful 3D packaging approach by virtue of the flexibility it offers in combining individual memory and logic packages vertically into a single solution in the industry standard 1.4mm total stacked package height. While current PoP technologies are effective in integrating multiple functions in a small form factor, reaching the next level of packaging bandwidth and performance in more advanced mobile devices drive advancements in the stacked package profile height below 1.0mm as well as tighter substrate line/space capability.

STATS ChipPAC's eWLB PoP technology offers customers significant performance, cost and height advantages over traditional substrate-based PoP technology. By utilizing eWLB's fan-out wafer level packaging approach, STATS ChipPAC has been able to reduce the bottom PoP package height to less than 0.5mm. eWLB PoP is available in either a single or double-sided configuration and provides a flexible integration platform for stacking a wide range of memory packages on top with a final stacked package height below 1.0mm.

"With eWLB we are able to offer a next-generation 3D PoP technology that achieves heterogeneous die integration and higher input/output (IO) density in a significantly smaller footprint than is possible today with standard PoP and flip chip technology. The maximum benefits of eWLB PoP can be achieved through a co-design process with our customers to optimize the functional performance of this ultra thin 3D package," said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC. "This is the thinnest 3D PoP solution available in the industry today and it delivers significant cost and performance advantages for our customers."

With high-performance and power-efficient capabilities in an inherently small, ultra-thin package profile, eWLB has been a technology enabler for advanced mobile applications such as smartphones, media tablets and cloud computing. STATS ChipPAC has shipped over 200 million eWLB units at a rapidly increasing run rate and is in volume production with a large number of eWLB package architectures including small die, large die, multi-die and multi-layer designs.

"eWLB has proven to be a scalable advanced technology that opens up a number of opportunities for our customers in terms of product design. In addition to mobile applications, there has been a growing interest from customers in computing applications where fanning out the device interconnection using eWLB technology can reduce substrate complexity and costs. eWLB is also well-suited for the microcontroller market where reducing cost and form factor are a priority," said Hal Lasky, Executive Vice President and Chief Sales Officer, STATS ChipPAC.

STATS ChipPAC will be presenting the latest information on innovative 3D packaging solutions including eWLB, low cost copper column flip chip PoP technology and stacked die integration of RF packages at the IMAPS International Conference and Exhibition on Device Packaging that is being held March 5th - 8th, 2012 in Scottsdale, Arizona.

Forward-Looking Statements
Certain statements in this release are forward-looking statements that involve a number of risks and uncertainties that could cause actual events or results to differ materially from those described in this release. Factors that could cause actual results to differ include, but are not limited to, the timing and impact of the expected closure of our Thailand facility as well as the estimated associated cost for the closure; the amount of the property damage and business interruption insurance claim due to flooding of our Thailand facility; the ability to shift production to other manufacturing locations, shortages in supply of key components and disruption in supply chain; general business and economic conditions and the state of the semiconductor industry; prevailing market conditions; demand for end-use applications products such as communications equipment, consumer and multi-applications and personal computers; decisions by customers to discontinue outsourcing of test and packaging services; level of competition; our reliance on a small group of principal customers; our continued success in technological innovations; pricing pressures, including declines in average selling prices; intellectual property rights disputes and litigation; our ability to control operating expenses; our substantial level of indebtedness and access to credit markets; potential impairment charges; availability of financing; changes in our product mix; our capacity utilisation; delays in acquiring or installing new equipment; limitations imposed by our financing arrangements which may limit our ability to maintain and grow our business; returns from research and development investments; changes in customer order patterns; customer credit risks; disruption of our operations; loss of key management or other personnel; defects or malfunctions in our testing equipment or packages; rescheduling or cancelling of customer orders; adverse tax and other financial consequences if the taxing authorities do not agree with our interpretation of the applicable tax laws; classification of our Company as a passive foreign investment company; our ability to develop and protect our intellectual property; changes in environmental laws and regulations; exchange rate fluctuations; regulatory approvals for further investments in our subsidiaries; majority ownership by Temasek Holdings (Private) Limited ("Temasek") that may result in conflicting interests with Temasek and our affiliates; unsuccessful acquisitions and investments in other companies and businesses; labour union problems in South Korea; uncertainties of conducting business in China and changes in laws, currency policy and political instability in other countries in Asia; natural calamities and disasters, including outbreaks of epidemics and communicable diseases; the continued trading and listing of our ordinary shares on the Singapore Exchange Securities Trading Limited ("SGX-ST"). You should not unduly rely on such statements. We do not intend, and do not assume any obligation, to update any forward-looking statements to reflect subsequent events or circumstances.

About STATS ChipPAC Ltd.
STATS ChipPAC Ltd. is a leading service provider of semiconductor packaging design, assembly, test and distribution solutions in diverse end market applications including communications, digital consumer and computing. With global headquarters in Singapore, STATS ChipPAC has design, research and development, manufacturing or customer support offices in 10 different countries. STATS ChipPAC is listed on the SGX-ST. Further information is available at Information contained in this website does not constitute a part of this release.

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