Asygn announces Tactyle-MX 2.0 for Imaging Systems, extending its A/M-S verification software

Grenoble – 27 Feb 2012 -- Asygn announces Tactyle-MX 2.0, an enhanced version of its analog/mixed-signal imager simulation software. This new release includes significant capabilities for the simulation of non-ideal effects, such as inter-pixel parasitics, parasitic coupling between pixels and interconnect and parametric variability across pixels.

"The simulation of a full, 1MPixel device, including the array, the surrounding circuitry, and with inter-pixel effects, takes about 1 hour”, explained Daniel Saias, Asygn's CEO,  “This is extremely fast and we believe that we are far ahead of our competition as far as the speed/precision tradeoff is concerned. This advantage will be maintained and may perhaps grow as work on multi-threading and multi-processing starts to bear fruit. Our technology is opening new possibilities for the functional and performance verification of highly repetitive A/MS systems."

Tactyle-MX is a member of Asygn's Tactyle family of analog/mixed-signal system-level simulators. At the heart of this technology are patent-protected algorithms that give fast simulation at the system level, though they do not allow (for reasons of efficiency) the simulation of transistors. Tactyle products are therefore integrated into a designer's existing design environment in a way that gives an easy path to other abstraction levels and to mixed-level simulations. Tactyle-MX is for use with highly regular systems, such as imagers and memories. These are typically represented as a hierarchical netlist (in SPICE format) for which the functional elements (the leaf nodes) are represented as system level models. The latter are developed by the basic Tactyle tool. This process, which is based on schematic capture and does not require any knowledge of behavioral language modeling (e.g. using Verilog-A/MS1 or VHDL-AMS2), includes a step that tunes the transistor-level model of an element to its system-level equivalent.

1. Verilog and Verilog-A/MS are trademarks of Cadence Design Systems, Inc.

2. VHDL and VHDL-AMS are IEEE standards 1076 and 1076.1 respectively.

Availability

Tactyle-MX 2.0 is available immediately. Use of the software requires work to integrate it into the designer's existing environment, and this must be discussed with Asygn before purchase.

About Asygn

Asygn is a Grenoble-based startup, specializing in the design and verification of analog/mixed-signal and RF systems. The company delivers application-focused solutions in order to deal with tough issues that traditional, generic approaches cannot handle. Asygn's solutions incorporate their own analog system level simulators, which provide major performance advantages. The company has had notable successes in the following applications: imaging arrays; mobile phone radios; MEMs and NEMs sensors; digital and fractional PLLs; high speed IOs.

Contact

Andrew Betts

+33 612 19 49 03

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