Axiom Launches UVM Debug Environment for SystemVerilog

Major New Functionality Added for UVM Debugging and Increased Productivity

Milpitas , California, February 21, 2012 --Axiom Design Automation, provider of fastest path to verification closure for semiconductor design, today announced its ground breaking UVM debug environment. Built on top of its best-in-class Designer debugging environment and tightly integrated with its MPSim SystemVerilog simulator, it has added significant new capability for developing and debugging UVM based SystemVerilog testbenches. UVM is the latest industry standard for developing testbenches and verification environment and is being widely adopted by the design community.

“SystemVerilog, especially UVM based environments seem to have become the testbench development methodology of choice amongst the industry, especially amongst our high end customers”, stated Tarak Parikh, Vice President of Products at Axiom Design Automation. “Our experience with our beta UVM customers however highlighted the complexities involved in creating and debugging UVM based testbenches and we responded accordingly. DesignerUVMtm is a complete UVM creation and debugging environment that incorporates several years of research into debugging testbench languages from AXIOM. As new standards emerge, we continue to invest in enhancing our technology to give our customers the most advanced and latest in performance and debugging capability”.

“Sibridge Technologies develops Verification IPs for some of the most advanced protocols”, said Rajesh Shah, CEO of Sibridge Technologies. “Most of our customers have started adopting UVM in their new designs. Our readiness of UVM ready VIP portfolio has enabled us to address new and existing customers. I am delighted to see Axiom develop special capability for UVM debugging. This UVM debugging capability is very timely and what the industry is looking for”.

DesignerUVM has many features including the ability to view UVM Schematic from the component hierarchy, check and create port connectivity, trace port drivers and receivers and trace any signal from a virtual interface to the real interface and through RTL. DesignerUVM completely automates the dumping and viewing of transactions and loads them into the waveforms. This is critical in getting to those last bugs.

MPSim is a complete Verilog/SystemVerilog verification platform with full support for SystemVerilog, OVM, VMM, and UVM.  It includes an advanced debugger in a single architecture resulting in high performance and throughput. MPSim also includes comprehensive coverage analysis that covers both functional and structural coverage. MPSim offers the most complete verification solution in a single unified kernel architecture for maximum performance. MPSim is production proven with several very large and complex chips taped out.

Axiom will be demonstrating DesignerUVM at the upcoming DVCon conference in San Jose, California.

About Axiom

Axiom Design Automation is a company focused on providing the best-in-class verification platform to address the growing complexity of today’s FPGAs, ICs, SOCs and systems. Axiom’s flagship product, MPSim is the state-of-the-art, industry proven high performance SystemVerilog simulator integrated with an advanced debugger, compiled testbench automation, multiple clock domain verification and comprehensive coverage analysis for quick verification closure. MPSim incorporates SystemVerilog and OpenVera testbench automation with SVA and coverage analysis in single kernel architecture for maximum performance. MPSim is fully compliant with industry standards such as VMM, OVM, UVM, UPF, etc. For more information please visit

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