1st Annual Event Featured at 2012 Design and Verification Conference (DVCon)

Monday, February 27
DoubleTree Hotel, San Jose, California
www.accellera.org

Accellera Systems Initiative™ is proud to sponsor The Design & Verification Conference & Exhibition (DVCon™). We are pleased to announce an exciting program of events for the first ever Accellera Systems Initiative Day on Monday, February 27!

Accellera Systems Initiative Day focuses on providing in-depth knowledge for our emerging and established standards to our user community. We are hosting a forum for SystemC users and conducting four tutorials on standards with sessions running concurrently throughout the day. We'll also host an interactive town hall lunch and discuss "What will success for the Accellera Systems Initiative look like?"

Accellera Systems Initiative Day is brought to you by our global sponsors: ARM, Cadence, CircuitSutra, Forte, Mentor Graphics, and Synopsys.

Agenda

View agenda matrix >

North American SystemC User Group (NASCUG) Meeting XVII

NASCUG provides a unique forum for sharing SystemC™ user experiences among industry, research and universities. NASCUG operates independently but works in collaboration with the Accellera Systems Initiative to provide open forums for promoting information exchange. Our goal is to make SystemC end-users more effective through shared knowledge, user interaction and collaboration.

NASCUG topics and user presentations:

• Accellera Systems Initiative: A New Synergy for Standards
• What does C++2011 mean to SystemC?
• Synchronization between a SystemC based off-line restbus simulator and a Hardware-In-the-Loop FlexRay network
• Extending Fixed Sub-Systems at the TLM Level — Experiences from the FPGA World
• A Generic Language for Hardware & Software, Are We There Yet? An Explorative Case Study Examining the Usage of SystemC for Multicore Programming

Participation is free. Find out more and register >

Tutorial: UVM (Universal Verification Methodology): Ready, Set, Deploy!

This tutorial will begin with an introduction to UVM™, concepts of structured verification methodology, base classes, resource configuration management, error handling, and report generation. It will continue with the UVM register package, including how to create and manage stimulus and checking at the register level. The morning session will conclude with a review of all of the topics, showing how they fit together in a complex SOC verification environment.