Simulation Driven IC and Electronic Systems Design at DesignCon
At the upcoming DesignCon conference and exhibits being held at the Santa Clara Convention Center on January 30 – February 2, Apache Design will be showcasing our advanced low-power solutions for chip-level power analysis, optimization, and sign-off, as well as comprehensive methodologies for Chip-Package-System convergence. As the newest member of the ANSYS family, both Apache and ANSYS will be demonstrating how the multi-physics engineering software portfolio of the combined companies enables innovative simulation-driven IC and electronic system development for power-efficient, high-performance and noise-immune electronic products. Visit both
Apache (#214) and ANSYS (#509) exhibit booths to find out how we are helping world’s top semiconductor companies reduce costs, mitigate risks, and accelerate product delivery.
Win an Apple iPad2!
Stop by the Apache and ANSYS booths to collect a unique puzzle piece at each location. When you have solved the puzzle by putting the pieces together, bring your completed puzzle to either the Apache or ANSYS booth to be entered into the daily raffle for an iPad2!
Register for a complimentary Expo Pass now.
Chip-Package-System (CPS) Workshops at DesignCon
Please join us for two educational CPS Workshops. Sponsored by Apache Design, a subsidiary of ANSYS, these interactive sessions will bring together leading semiconductor companies and system houses to share their expert perspectives and best practices on chip and package modeling, and system-level verification for SI, PI, EMI and thermal effects. For more information,
click here.
Register for your complimentary Expo Pass and select one or both workshops during the registration process. There is no cost to attend the workshops, but registration is required.
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Upcoming Events
Power Issues for Chip and Board Webinar
At your computer
January 31, 2012 at 11:00AM PST
DesignCon
Santa Clara, CA
January 31 - February 1, 2012
Chip-Package-System (CPS) Workshops
Santa Clara, CA
February 1, 2012
ISQED
Santa Clara, CA
March 21, 2012
In the News
Popular White Papers
- RTL Design-for-Power (DFP) Methodology
- Low Power Design Analysis
- Power and Noise Integrity for Analog/Mixed-Signal Designs
- PathFinder™: Solution for Full-chip IC ESD Integrity
- Advanced Modeling for Chip, Package, System Co-analysis/Co-optimization
- Power and Signal Line EM Design and Reliability Validation Challenges
- Technologies for Power, Signal, Thermal, and EMI Sign-off
To download White Papers from our website,
click here . Valid account required.
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