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Aldec Design and Verification Newsletter Q1, 2012
Catch up on the latest in Design and Verification at: http://www.aldec.com/newsletter/ Looking Back – and Ahead to the Next 25 YearsTwo years from now, Aldec will celebrate a milestone - 25 years of innovative service to the Electronic Design Automation industry. Working with designers in the field since the birth of EDA, Aldec has had a front row seat to witness the recent decades’ astonishing surge in technology. From smart phones to advances in medical safety and aviation, few outside the industry realize without the diligent electronics designer aided in the lab by innovative EDA tools - the life changing advances we take for granted today would not exist. Fewer EDA tool providers competing for their business (thanks to a steady stream of recent mergers and acquisitions) has left some customers asking if the future of EDA will hold less innovation, support and service – at a higher price. At Aldec, our customer-centric business model ensures that we will continue to revolutionize the industry with exciting tools delivered to serve real-world needs of our customers. Riviera-PRO Delivers Complete Support for UVM, Enabling VMM and OVM InteroperabilityRiviera-PRO™ offers complete support for the Universal Verification Methodology (UVM) Version 1.1, and enhances the SystemVerilog verification methodology by providing extended language construct support and adding debugging and productivity features in the waveform. The new language construct enhancements, based on an industry accepted IEEE 1800™-2009 standard, enable customers to do extensive debugging and provide a path to support for UVM together with previous Open Verification Methodology (OVM) and alternative Verification Methodology Manual (VMM) methodologies. Read More Active-HDL 9.1 Supporting Simulation of the Newest FPGA DevicesThe latest release of Active-HDL™, an award-winning HDL-based FPGA Design and Simulation solution, supports design creation and simulation of the newest industry-leading FPGA devices from Altera®, Atmel®, Lattice®, Microsemi™ (Actel), Tabula, Quicklogic® and Xilinx®. Known to FPGA designers as a tool-of-choice for ease and convenience (with design creation, documentation, code coverage and simulation bundled into one product) the latest release of Active-HDL includes even more benefits such as: Read More OS-VVM™ named Product of the Week by Electronics World for Delivering Randomization Capabilities to VHDL Designers
Hardware Visibility-based Debugging (HVD™) Technology, Provides 100% Visibility During Hardware EmulationBuilt into the emulation solution, Aldec’s HVD (Hardware Visibility-based Debugging) technology analyzes RTL code to identify the minimal set of debugging probes that must be present in the emulation hardware to guarantee 100% visibility. During the emulation runtime, the HVD based data extender calculates any design probes that have not been captured directly from the emulator. For a typical SoC design, this reduces the amount of data required to be preserved and captured from the emulator to 30% (70% saving). Additionally, both dynamic and static probes from emulation can be visualized in the Riviera-PRO waveform viewer preserving the original signal names and hierarchy paths and complete traceability to the designs RTL source code. Read More Advanced Standalone Reporting to Facilitate Design ReviewsWith the latest release of ALINT, product version 2012.01, even completely new users can create and distribute interactive reports in a few minutes without the knowledge of any details about the design that is being checked, tool’s configuration, commands, and command line switches. Typically it takes less than one hour to set up and check a relatively complex design and deploy the appropriate interactive report on the corporate intranet or version control system. Read More Standardized Coverage Driven VerificationDo you think that vendor specific coverage database format is not sufficient when it comes to overall coverage driven verification? Coverage metrics can come from different sources such as simulation, formal verification, equivalence checking, static design checking etc. There are different vendors that provide tools/solution for each of these categories. But each vendor has their own proprietary coverage database format which keeps users from mixing verification management tool and simulator from different vendors in their flow. Read More Aldec.com delivers New Features and Enhanced User Functionality
We invite you to click here to take a tour today, and take advantage of the 'Feedback' button to share your thoughts on the new site. We appreciate your feedback as we continually seek to improve our customer support experience. DO-254 Training Seminar Results: Exceeding the ExpectationsThe recent DO-254 training seminar held Las Vegas, NV was well received by attendees. Notable firms in attendance included BAE Systems, Eaton, L3 Communications, Moog and Thales Avionics as well as other leading avionics companies representing four different countries. Attendees learned how to create and organize requirements by functional elements such that they are traceable and verifiable, as well as how to develop normal and robust test cases such that they are re-usable in simulation and in-circuit tests. Read More
Product UpdatesALINT™ 2012.01The new release of ALINT brings valuable tools for efficient project collaboration and information sharing across your organization. These new tools include:
In addition, we have implemented numerous productivity features based on requests coming from our customers – make sure to leverage all these benefits as soon as the new build is available! Riviera-PRO™ 2012.02 (Available February 2012)The last release of Riviera-PRO, version 2011.10, delivered a pack of new productivity features, support for the new language constructs in VHDL’2008 and SystemVerilog’2009, and incremental updates of the verification libraries shipped with the tool. In 2012, Aldec continues developing Riviera-PRO at the traditional fast pace, delivering 3 major releases per year. The next version, Riviera-PRO 2012.02, scheduled to arrive in February’2012, is coming with an array of new debugging features. For example:
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Open Source - VHDL Verification Methodology (OS-VVM™), recently named Electronics World Product of the Week, delivers advanced verification test methodologies, including Constrained and Coverage-driven Randomization, as well as Functional Coverage, providing advanced features to VHDL design engineers while enabling them to continue to develop using VHDL.
Aldec.com has a new look, fresh content, new features and enhanced functionality. With a new site fully integrated with Aldec's contact database, visitors will no longer have to register for every download. Instead (once logged in) users will have access to Aldec’s Support Portal, as well as Downloads, Registrations and other Resources.
