Date: Thursday, January 26, 2012
(Europe) Time: 3:00 PM - 4:00 PM CET
(US) Time: 11:00am – 12:00pm PST
To register, please visit aldec.com/events.
Open Source - VHDL Verification Methodology (OS-VVM ) provides advanced verification capabilities to VHDL teams. Attend this webinar and learn how to add functional coverage, constrained random, and coverage driven random methods to your current testbench.
OS-VVM has a straight forward usage model that allows you to add functional coverage, constrained random, and coverage driven random features to your current testbench in part or in whole. So add functional coverage to your testbench today - you need this even with directed tests. Add constrained random or coverage driven random when and where you need it. Even mix directed, algorithmic, file-based, constrained random, and coverage driven random methods.
OS-VVM is open source package based. It compiles under VHDL-2008 or VHDL-2002 (with minor adaptations), so you can use it today.
- Functional Coverage
- Code Coverage is not Enough
- Test Done = Test Plan Executed
- Why you need functional coverage
- Capturing Point Coverage
- Capturing Item Coverage
- Intelligent Coverage
- Mixing in other code
- Demonstration - seeing is believing