Aldec and SynthWorks: OS-VVM: Open Source - VHDL Verification Methodology, Jan. 26

Date: Thursday, January 26, 2012

(Europe) Time: 3:00 PM - 4:00 PM CET

(US) Time: 11:00am – 12:00pm PST

To register, please visit

Open Source - VHDL Verification Methodology (OS-VVM ) provides advanced verification capabilities to VHDL teams.   Attend this webinar and learn how to add functional coverage, constrained random, and coverage driven random methods to your current testbench. 

OS-VVM has a straight forward usage model that allows you to add functional coverage, constrained random, and coverage driven random features to your current testbench in part or in whole.  So add functional coverage to your testbench today - you need this even with directed tests.  Add constrained random or coverage driven random when and where you need it.  Even mix directed, algorithmic, file-based, constrained random, and coverage driven random methods.

OS-VVM is open source package based.  It compiles under VHDL-2008 or VHDL-2002 (with minor adaptations), so you can use it today. 


  • Introduction
  • Methodology
  • Functional Coverage
  • Code Coverage is not Enough
  • Test Done = Test Plan Executed
  • Why you need functional coverage
  • Capturing Point Coverage
  • Capturing Item Coverage
  • Randomization
  • Intelligent Coverage
  • Mixing in other code
  • Demonstration - seeing is believing

Review Article Be the first to review this article

Featured Video
Design Verification Engineer for intersil at Morrisville, North Carolina
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, California
Applications Engineer for intersil at Palm Bay, Florida
Upcoming Events
NVIDIA’s GPU Technology Conference (GTC) at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - Mar 26 - 29, 2018
ESC Conference Boston at boston MA - Apr 18 - 19, 2018
IEEE Women in Engineering International Leadership Conference at 150 W San Carlos St San Jose CA - May 21 - 22, 2018
DownStream: Solutions for Post Processing PCB Designs

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise