On Demand: Optimize Circuit Design Yield and Improve Reliability with Advanced Verification Tools

This webinar will demonstrate how to use Calibre PERC to improve design quality and mitigate otherwise difficult to find errors within design and verification flows. Ensuring reliability and protecting against ESD, Latch-up, and other EOS events can be challenging, particularly when multiple power domains and thin-oxide gates are used extensively. Detailed SPICE/Mixed-Mode simulation is an often used, but costly step.  Learn how Calibre PERC delivers an easy to use verification solution that looks at the entire design in context and answers specific reliability issues quickly and effectively.

You will learn:

o    How to detect sources of reliability issues within
      your designs

o    How to effectively verify signal paths in
      multi-power domain designs

o    Benefits of voltage dependant, and voltage
      aware checks - both on the topological
      representation of your design (netlist),
      and the physical layout




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