"Improvements in the latest PAC-Designer 6.2 and Lattice Diamond 1.4 software tools raise our customers' ability to design and simulate Platform Manager devices to new levels," said Shyam Chandra, Lattice Product Marketing Manager for Mixed Signal Products. "The ability to simulate external pins enables platform-level logic simulation that significantly increases the likelihood of first time success, resulting in reduced time to market."
Comprehensive Analog and Digital Design Flow
PAC-Designer 6.2 software provides an easy to use GUI-based design methodology for configuring the Platform Manager's analog sections. To implement more advanced digital board management functions, Lattice Diamond Verilog/VHDL design tools are available for use with the same design. Once a design is implemented, a complete simulation environment is created that includes automatic stimulus template file generation.
PAC-Designer 6.2 software includes reference designs specifically targeted for the Platform Manager development kit. More reference designs compatible with Platform Manager devices are available on the Lattice website at http://www.latticesemi.com/products/powermanager/platformmanager/.
Third Party Design Tool Support
The integrated PAC-Designer 6.2 and Lattice Diamond 1.4 software both include the Synopsys Synplify Pro advanced FPGA synthesis for Windows. Aldec's Active-HDL Lattice Edition II simulator is also included for Windows.
In addition to the tool support provided by the OEM versions of Synplify Pro and Active-HDL, Lattice devices are also supported by the full versions of Synopsys Synplify Pro and Aldec Active-HDL. Mentor Graphics ModelSim SE and Precision RTL synthesis also support Lattice devices.
About the Platform Manager Family
The innovative Platform Manager product family consists of two devices, the LPTM10-1247 and LPTM10-12107. The LPTM10-1247 device can monitor 12 voltage rails and supports 47 combined digital inputs and digital outputs, while the LPTM10-12107 monitors up to 12 voltage rails and supports 107 combined digital inputs and digital outputs. Functionally, these devices include both a power management section and a digital board management section. The power management section consists of a programmable threshold, precision differential input comparator block with an accuracy of 0.7%, a 48-macrocell CPLD, programmable hardware timers, a 10-bit analog to digital converter and a trim block for the trimming and margining of supplies. The digital board management section consists of a 640-LUT FPGA and programmable logic interface I/O.
Pricing and Availability
PAC-Designer 6.2 and Lattice Diamond 1.4 software are available immediately for free download from the Lattice website at http://www.latticesemi.com/products/designsoftware/pacdesigner/index.cfm. Once downloaded and installed, PAC-Designer 6.2 software requires no separate license file. Lattice Diamond 1.4 software can be used with either the Lattice Diamond free license or the Lattice Diamond subscription license. The Lattice Diamond free license can be immediately generated upon request from the Lattice website and provides no cost access to the Platform Manager product family as well as many other popular Lattice devices such as the MachXO2 and MachXO PLD families, the LatticeXP2 FPGA family and the LatticeECP2 FPGA family. The Lattice Diamond free license enables Synopsys Synplify Pro for Lattice synthesis as well as the Aldec Lattice Edition II mixed language simulator.
About Lattice Semiconductor
Lattice is the source for innovative FPGA, PLD and programmable Power Management solutions. For more information, visit www.latticesemi.com. Follow Lattice via Facebook, RSS and Twitter.
Lattice Semiconductor Corporation, Lattice (& design), L (& design), PAC-Designer, ispClock, LatticeXP2, Lattice Diamond, MachXO, MachXO2, LatticeECP2, Platform Manager and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.
GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.
EDITORIAL/READER CONTACT: Brian Kiernan Corporate Communications Manager Lattice Semiconductor Corporation 503-268-8739 voice 503-268-8688 fax Email Contact