Mentor Verification Horizons Q3 2011

We’re finally doing it. My wife and I have been in our house for 13½ years and we’re finally redoing our kitchen, which my wife has wanted to do for about 11 years now. When we had the house built, we chose to limit our budget to keep “expensive” from turning into “exorbitant,” and we’ve been living with formica countertops and a linoleum floor ever since. It’s rather exciting seeing the first steps of converting these into granite and hardwood. As you might imagine, I find myself thinking of how this relates to upgrading a verification methodology because I’m sure that, by now, you know that that’s how my mind works.

When a project like this comes up, my wife and I work well together. I tend to go overboard and want to buy new appliances, add new cabinets and maybe even throw in a new “island” with a sink. Dee, on the other hand, is the more practical one so we’ll be keeping the appliances and cabinets. We are also removing the wallpaper and having the walls painted. So, we’ve got some “legacy IP” we need to work with, but we’ll be able to integrate it all with the new stuff and have a much more useful – and modern – kitchen than we had before. Keep this analogy in mind as you read the following articles.

Our feature article this time comes from my friend Andy Meyer, a fellow Verification Technologist here at Mentor. In “ Graph-Based IP Verification in an ARM SoC Environment ,” Andy shows how the use of graph-based verification methods not only serve to upgrade the quality of your block-level verification efforts, but also how combining graphs with your UVM environment makes it easier to extend block-level components into an SoC test environment. As you’ll see, this approach lets you use reuse your block-level verification IP both to ensure that your design blocks are functioning properly in the SoC and also easily construct a complex SoC verification environment from the block-level components.

Our next article comes from Infineon who share their thoughts on how to “ Use Scripting Language in Combination with the Verification Testbench to Define Powerful Test Cases .” This article shows how to use Tcl (or any scripting language) to simplify the task for designers of customizing testbenches. The article discusses both VHDL and OVM testbenches, but the technique is applicable to UVM as well.

When I was in college, I recall my dad, who was an analog designer, telling me that “it’s an analog world” and that my digital exploits would eventually run into this reality. The truth of my dad’s wisdom is evident in our next article, in which “ STMicroelectronics Engineers Find Mixed Analog-Digital Verification Success with OVM and Mentor Graphics Questa ADMS Simulator .” In it, you’ll see how STMicro created analog-friendly OVM verification IP that allowed them to take advantage of OVM in generating realistic analog traffic via Questa ADMS.

We next share a couple of “how to” articles on some of the finer points of OVM/UVM testbench design. The first, “ Polymorphic Interfaces: An Alternative for SystemVerilog Interfaces ,” by my colleague Shashi Bhutada, builds on prior work that explores the use of abstract classes to replace virtual interfaces for connecting your OVM/UVM testbench to the DUT. This particular application shows how this technique allows you to create a single driver class that can use different specializations of an interface without having to rewrite anything. This is followed by our monthly article from the UVM/OVM Online Verification Methodology Cookbook at the Verification Academy. This article shows .

In the Partners’ Corner for this issue, our friends from Test and Verification Solutions share their experiences in helping Dialog Semiconductor to adopt OVM for their verification solution. “
Successful Adoption of OVM and What We Learned Along the Way ” will give you some insight into what you may expect if you’re thinking of doing the same.

Last, but not least, my colleague Darron May asks the important question, “ Process Management: Are You Driving in the Dark with Faulty Headlights ?” This article builds on Darron’s previous article about Questa’s Unified Coverage Database to show how we’ve developed additional technologies in our Verification Management tool to turn the data in the UCDB into valuable information for you to measure and manage your verification process.

I’m concluding this welcome message in my kitchen. The new countertops will be installed in a few days, but the walls already have a coat of primer on them. The process is underway and we’re really looking forward to it. One of the big additions for me is the new flat-screen high-definition television I set up this afternoon. If you have a vision of where you want to be, the key is to do your planning up front, take it one step at a time, and don’t forget to enjoy the experience. That works whether you’re upgrading your kitchen or your verification process. I hope you enjoy this issue.

Respectfully submitted,

Tom Fitzpatrick
Editor, Verification Horizons

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