Latest News from Apache Design - November 2011

Apache Launches RTL Power Model (RPM™) for Predicting IC Behavior

RTL Power Model is a first-in-class innovative technology that enables integrated ultra-low-power design methodology by bridging the power gap between RTL design and physical implementation.

The new technology accurately predicts integrated circuit (IC) power behavior at the RTL level with consideration for how the design is physically implemented. As a result, the technology helps to enable chip power delivery network (PDN) and IC package design decisions early in the design process, as well as to ensure chip power integrity sign-off for sub-28nm ICs.

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Low Power, High Performance

The acquisition of Apache increases ANSYS capabilities for designing low-power electronics devices while satisfying ever-increasing performance requirements.

ANSYS simulation technologies address complex multiphysics challenges and enable Simulation-Driven Product Development. As semiconductor devices pervade every aspect of our lives, in cars, smartphones and smart-meters, their impact on the end systems (and vice versa) is becoming a key design challenge for our customers. The combination of Apache’s chip-level power, thermal, signal and EMI modeling solutions, along with ANSYS package and system electromagnetic, thermal/fluids and mechanical simulation platforms, will enable faster convergence for the next generation of low-power, energy-efficient designs.

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  • RTL Design-for-Power (DFP) Methodology
  • Advanced Modeling for Chip, Package, System Co-analysis/Co-optimization
  • Technologies for Power, Signal, Thermal, and EMI Sign-off for Chip-Package-PCB Designs
  • Power and Signal Line EM Design and Reliability Validation Challenges
  • Analysis of Low-Power Designs with Power Gate (MTCMOS) Circuits Using RedHawk™

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