Calypto Exhibits at ARM TechCon and Offers Class on RTL Verification, Oct. 25

SANTA CLARA, CA -- (MARKET WIRE) -- Oct 24, 2011 -- ARM TechCon 2011, October 25, Santa Clara, CA

Calypto® Design Systems, Inc., the leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) power optimization, announced that Nikhil Sharma, Vice President of Applications Engineering and Services, will speak on Formal Verification of RTL Changes for Intellectual Property (IP) Hardening at ARM TechCon 2011, in Santa Clara, CA, USA, Tuesday, October 25. In addition, during the ARM TechCon Expo on the same day, Calypto representatives will be available to talk about its software platforms, Catapult® HLS (High Level Synthesis), SLEC® (Sequential Logic Equivalence Checking) and PowerPro®, which enable ESL design, dramatically improve design quality and reduce power consumption of System-On-Chip (SOC) devices.

Tuesday, October 25, 2011, 4:10pm-5:00pm
Room 207
Formal Verification of RTL Changes for IP Hardening

Tuesday, October 25, 2011, 10:15am-7pm
Stand #5
Santa Clara Convention Center
Santa Clara, CA, USA

For more information
For more information about ARM TechCon, please visit
For more information about Calypto please visit at
To make an appointment with Calypto at ARM TechCon, please email Email Contact.

About Calypto
Calypto® Design Systems, Inc. is the leader in ESL hardware design and RTL power optimization. Calypto, whose customers include Fortune 500 companies worldwide, is a member of the ARM Connected Community, Cadence Connections program, the IEEE-SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, Si2 and is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan and North America.

More information can be found at

Catapult, Calypto, PowerPro and SLEC are trademarks of Calypto Design Systems Inc.
All other trademarks are property of their respective owners.


Add to Digg Bookmark with Add to Newsvine


Press Contact:
Georgia Marszalek
ValleyPR, LLC for Calypto

Email Contact 

Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs

Featured Video
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, California
Applications Engineer for intersil at Palm Bay, Florida
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Design Verification Engineer for intersil at Morrisville, North Carolina
Upcoming Events
Decoding Formal Club Meeting Featuring Formal Talks by ArterisIP and Cisco at 2099 Gateway Place, Suite 560 San Jose CA - Mar 20, 2018
NVIDIA’s GPU Technology Conference (GTC) at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - Mar 26 - 29, 2018
ESC Conference Boston at boston MA - Apr 18 - 19, 2018
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise