SANTA CLARA, CA -- (MARKET WIRE) -- Oct 24, 2011 -- ARM TechCon 2011, October 25, Santa Clara, CA
Calypto® Design Systems, Inc., the leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) power optimization, announced that Nikhil Sharma, Vice President of Applications Engineering and Services, will speak on Formal Verification of RTL Changes for Intellectual Property (IP) Hardening at ARM TechCon 2011, in Santa Clara, CA, USA, Tuesday, October 25. In addition, during the ARM TechCon Expo on the same day, Calypto representatives will be available to talk about its software platforms, Catapult® HLS (High Level Synthesis), SLEC® (Sequential Logic Equivalence Checking) and PowerPro®, which enable ESL design, dramatically improve design quality and reduce power consumption of System-On-Chip (SOC) devices.
Tuesday, October 25, 2011, 4:10pm-5:00pm
Formal Verification of RTL Changes for IP Hardening
Tuesday, October 25, 2011, 10:15am-7pm
Santa Clara Convention Center
Santa Clara, CA, USA
For more information
For more information about ARM TechCon, please visit http://e.ubmelectronics.com/armtechcon/index.html.
For more information about Calypto please visit at www.calypto.com.
To make an appointment with Calypto at ARM TechCon, please email Email Contact.
Calypto® Design Systems, Inc. is the leader in ESL hardware design and RTL power optimization. Calypto, whose customers include Fortune 500 companies worldwide, is a member of the ARM Connected Community, Cadence Connections program, the IEEE-SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, Si2 and is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan and North America.
More information can be found at www.calypto.com.
Catapult, Calypto, PowerPro and SLEC are trademarks of Calypto Design Systems Inc.
All other trademarks are property of their respective owners.
Press Contact: Georgia Marszalek ValleyPR, LLC for Calypto +1-650.345.7477 Email Contact