Aldec with Imperas Webinar: Transaction Level Co-Emulation with Virtual Platforms, Oct. 13

Date:      Thursday, October 13, 2011

Time:      11:00 am - 12:00 pm PDT (US)        

Click here to Register.  

__________________________________ 

Date:      Thursday, October 13, 2011

Time:      3:00 pm - 4:00 pm CET (Europe)

Click here to Register.

__________________________________

Abstract:
Virtual platforms play a significant role in system level development, but require integration with ultra-fast emulation systems for HW/SW co-verification.  In this webinar we will introduce the new integration of Aldec's Transaction Level Emulation System with Imperas' OVPsim virtual platform simulator.  Hardware and software design teams are now able to implement virtual models of processors, memory and peripheral modules while the RTL modules run in the emulator board.  This integration provides a high performance solution, ideal for early HW/SW co-development and architectural exploration.

Agenda

• Virtual Platforms: What are the benefits?

• SoC Design Flow with Virtual Platforms

• Imperas’ OVP and OVPsim

• TLM 2.0 Interface

• Integration of Aldec’s Emulation System with OVP and OVPsim

• Processor Debugging, Memory Debugging, Hardware Debugging

• Live Demonstration 

Presenters:

Louie de Luna, Aldec Product Manager

Larry Lapides, Imperas VP Sales

Piotr Czak, Applications Engineer

Time not fit your Schedule or Time Zone?

We invite you to proceed with registration. Following the Webinar, all registrants are emailed a link to download the recorded Webinar Presentation to view at their convenience.

To register or view more Aldec Events, please visit http://www.aldec.com/events




Review Article Be the first to review this article
CST: Webinar November 9, 2017

Synopsys: Custom Compiler

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Jobs
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Upcoming Events
25th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2017) at Yas Viceroy Abu Dhabi Yas Marina Circuit, Yas Island Abu Dhabi United Arab Emirates - Oct 23 - 25, 2017
ARM TechCon 2017 at Santa Clara Convention Center Santa Clara CA - Oct 24 - 26, 2017
MIPI DevCon Bangalore 2017 at The Leela Palace Bengaluru India - Oct 27, 2017
MIPI DevCon Hsinchu City 2017 at Sheraton Hsinchu Hotel Taiwan - Oct 31, 2017
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise