"FPGA-Based Prototyping is Hard to Do—Or is It?" N.A. Cadence Seminars: Oct. 25 to Nov. 15
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A technical seminar presented by Cadence featuring the recently introduced System Development Suite, with special guest Altera

Space is limited! Register today at  http://www.secure-register.net/cadence/sysr_seminar_q411

Overview:

It’s all about the software; getting to tapeout is often not the biggest problem anymore! Software has started to dominate development costs and schedules; it has become a product differentiator and, if done right, a competitive advantage. Therefore, it’s critical to get a head-start on software development and hardware/software integration, long before the actual silicon is available. How critical? A recent IBS survey estimates that a 9-12–month delay in system integration and bring-up will result in a revenue loss of $50-100M.

Does System-Level Design and Validation Really Have to be So Hard?

In this seminar, we will provide a fresh perspective on how using the right methodologies and tools, at the right time, will speed up system development and validation by 50% or more.

The FPGA-based prototyping methodology is used widely as a platform for early software development, but has earned the reputation of being difficult to do. You will learn first-hand that it doesn’t have to be difficult at all. The new Cadence Rapid Prototyping Platform can dramatically improve prototyping bring-up time and make FPGA-based prototyping much easier to use and to deploy.

Space is limited! Register today at  http://www.secure-register.net/cadence/sysr_seminar_q411

Dates and Locations:

  • Tues, Oct 25, 2011, 1:00 - 4:15pm, Irvine
  • Thurs, Oct 27, 2011, 1:00 - 4:15pm, Austin
  • Tues, Nov 8, 2011, 1:00 - 4:15pm, Chelmsford
  • Thurs, Nov 10, 2011, 1:00 - 4:15pm, Ottawa
  • Tues, Nov 15, 2011, 1:00 - 4:15pm, San Jose

Agenda

  • 1:00-1:15pm   Introduction and Overview
  • 1:15-1:30pm   Cutting System Development Time in Half With the Cadence System Development Suite
  • 1:30-2:15pm   FPGA-Based Prototyping: Does it Really Have to be This Difficult?
  • 2:15-2:30pm   Break and Discussion
  • 2:30-3:00pm   Live Demonstration of the Cadence Rapid Prototyping Platform
                            – Step-by-step implementation of an embedded system SoC design    
                            – Boot and execute LINUX
  • 3:00-3:30pm   Increasing Prototyping Productivity and Performance Through FPGA Architecture and Design Tools  (Altera)
  • 3:30-4:00pm   Another Type of Prototyping: The Cadence Virtual System Platform
  • 4:00-4:15pm   Close

Space is limited! Register today at  http://www.secure-register.net/cadence/sysr_seminar_q411




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