DUBLIN, Ireland, September 20th 2011- Duolog Technologies, the award-winning developer of IP and SoC integration products, is partnering with Cadence to present a joint webinar featuring automated solutions to many of the problems commonly associated with HW/SW integration. The webinar, scheduled for October 11th, will feature an interactive demonstration of a complete design and verification environment implemented using the Duolog Socrates and Cadence Incisive Enterprise Simulator products. The demonstration will clearly illustrate how subtle bugs caused by miscommunication at the HW/SW and testbench/DUT interfaces can affect the quality of the system and produce alarming results. The Duolog and Cadence teams will demonstrate how an effective combination of advanced verification methodologies such as UVM and formal register management techniques can eliminate these bugs from the HW/SW integration process.
Topic: Automating UVM to Tackle Insidious HW/SW Bugs.
- David Murray, Chief Technology Officer, Duolog Technologies.
- Adam Sherer, Verification Product Management Director, Cadence.
When: Tuesday, October 11th, 2011 @ 9:00 AM PDT / 5:00 PM BST.
Duration: Approximately one hour.
Who Should Attend: Design & Methodology engineers/managers who have encountered misalignment and synchronization errors in the HW/SW interface and wish to eliminate them in the future.
About Duolog Technologies: Duolog Technologies is a leading developer of EDA tools that address the increasingly complex challenges of IP integration. We enable our customers to deliver integrated systems more quickly and cost effectively than their competitors. Our innovative products and solutions allow for maximum productivity and control throughout the entire system lifecycle.
For further information on Duolog, please contact: