Duolog + Cadence Webinar: Automated UVM Solutions to HW/SW Integration Problems, Oct. 11

DUBLIN, Ireland, September 20th 2011- Duolog Technologies, the award-winning developer of IP and SoC integration products, is partnering with Cadence to present a joint webinar featuring automated solutions to many of the problems commonly associated with HW/SW integration. The webinar, scheduled for October 11th, will feature an interactive demonstration of a complete design and verification environment implemented using the Duolog Socrates and Cadence Incisive Enterprise Simulator products. The demonstration will clearly illustrate how subtle bugs caused by miscommunication at the HW/SW and testbench/DUT interfaces can affect the quality of the system and produce alarming results. The Duolog and Cadence teams will demonstrate how an effective combination of advanced verification methodologies such as UVM and formal register management techniques can eliminate these bugs from the HW/SW integration process.    

Topic: Automating UVM to Tackle Insidious HW/SW Bugs.

Presenters:

  • David Murray, Chief Technology Officer, Duolog Technologies.
  • Adam Sherer, Verification Product Management Director, Cadence.

When: Tuesday, October 11th, 2011 @ 9:00 AM PDT / 5:00 PM BST.

Duration: Approximately one hour.

Who Should Attend: Design & Methodology engineers/managers who have encountered misalignment and synchronization errors in the HW/SW interface and wish to eliminate them in the future.

Registration: http://www.duolog.com/webinar-automating-uvm-to-tackle-insidious-hwsw-bugs/

About Duolog Technologies: Duolog Technologies is a leading developer of EDA tools that address the increasingly complex challenges of IP integration.  We enable our customers to deliver integrated systems more quickly and cost effectively than their competitors.  Our innovative products and solutions allow for maximum productivity and control throughout the entire system lifecycle.  



For further information on Duolog, please contact:
Sally Kenny
+353-91-730 879
Email Contact 

www.duolog.com




Review Article Be the first to review this article

Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Diversity: Really, who cares
More Editorial  
Jobs
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
DDR 3-4-5 Developer with VIP for EDA Careers at San Jose, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Senior Methodology Automation Engineer for EDA Careers at San Jose, CA
Proposal Support Coordinator for Keystone Aerial Surveys at Philadelphia, PA
Upcoming Events
11th International Conference on Verification and Evaluation of Computer and Communication Systems at 1455 DeMaisonneuve W. EV05.139 Montreal Quebec Canada - Aug 24 - 25, 2017
The Rise of Mechatronics at Dassault Systèmes San Diego 5005 Wateridge Vista Drive San Diego CA - Sep 12, 2017
The Rise of Mechatronics at Buca di Beppo - Pasadena 80 West Green Street Pasadena CA - Sep 13, 2017
DownStream: Solutions for Post Processing PCB Designs
S2C: FPGA Base prototyping- Download white paper
TrueCircuits: UltraPLL



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy