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Understanding Grounding
Misunderstanding how ground is implemented in circuit simulation is one of the most common misuses of electromagnetic (EM) simulators and their results. This white paper discusses the defi nition of ground in EM simulators and how to correctly choose among various grounding options, a topic of special importance to designers using the results in a circuit simulator. Many modern simulators now support the notion of local grounding, where different ports can use different ground defi nitions. New features in AWR’s AXIEM™ 2009 3D planar EM simulator offer extensive sources/ports and de-embedding options, including internal edge, fi nite difference/gap and extraction ports, and per-port, coupled line and mutual group de-embedding. AWR Corporation
A Plethora of Ports:
Electromagnetic (EM) simulation technology software has come a long way since it first became popular for microwave and RF circuit design back in the 1980s. With the sophistication of today’s EM tools, it is sometimes difficult to remember how limited those early simulators were. The author is old enough to remember when a challenging problem for a 3D planar simulator consisted of a coupled-line filter with 1000 unknowns and 3D finite element simulators were stressed by a simple multi-layer via transition in a package. AWR Corporation
A Basic Mathematical
Electronic Design Automation (EDA) has been one of the great enabling technologies for modern electronics, including the class of analog circuits classified by their operating frequencies: RF/wireless, microwave, millimeter-wave, etc. Initially distinct and discrete software tools were developed for (logical) circuit simulation and (physical) layout, and these were later augmented by physical verification (DRC & LVS), system simulation, and electromagnetic analysis (EM). Later still, all of these tools came together under unifying environments providing a common database and standardized graphical (schematic) entry. AWR Corporation
High-Speed Serial Backplane
The benefit to having high-frequency design tools resident on a Vector Network Analyzer (VNA) does not become obvious until the time comes to compare simulation to measurements. At this point, the advantage of a more streamlined work flow -- without the impediment of transferring data to a simulator running on a separate PC or workstation - becomes clear. To illustrate the benefit of such a novel, integrated solution (AWR’s Microwave Office software “inside” the Anritsu VectorStar VNA), this application note follows the design flow for a high-speed serial backplane. AWR Corporation
Clock and Reset Ubiquity:
Today’s SoC integrates a collection of peripherals, memory, graphics, networking and I/O components that originate from a multitude of sources. It could comprise designs from within the company, from other companies or from third-party IP vendors. These independently developed components come together to enable a rich feature set for the SoC. However, accompanying this abundance of features is a significant amount of complexity that needs to be correctly and efficiently handled to render the integration successful. One such source of complexity is that components operate at clock frequency ranges that may be very different from those of their counterparts. The existence of these multiple clock domains and the need for them to exchange information creates a hotbed for CDC bugs to thrive. As a result, CDC verification becomes critical to ensure that metastability is not introduced in the design. In this article, we provide several situations with varying set of examples that showcase the challenges in CDC verification. Real Intent, Inc.
Design Flow for Base
Automated synthesis of microwave devices has been gaining in popularity in CAE applications over the past decade. Antenna Magus now brings this capability to the fi eld of antenna design. Antenna Magus provides a structured catalog of antennas (monitor image below) with concise documentation, robust design algorithms, and export models. AWR Corporation
Design and Synthesis
Next generation high power, high and width electronic devices rely on well-designed RF/microwave components for peak performance. In the specialized world of RF and microwave engineering, the design and development of power amplifi ers (PAs) is a specialty within a specialty that requires many years of focused engineering experience and a suitable collection of test and measurement (T&M) equipment. AWR Corporation
High-Power Amplifier
SYMMIC from CapeSym is a template-based thermal simulator that has been optimized for monolithic microwave integrated circuit (MMIC) design. This application note demonstrates the integration of Microwave Office and SYMMIC. The integration is script-based and requires minimum manual ntervention as compared to non-integrated thermal solvers. The example used here is an extension of the MMIC high power amplifier (HPA) example that is part of the standard Microwave Office set of examples. AWR Corporation
Design and Optimization
3D electromagnetic (EM) simulators are commonly used to help design board-to-chip transitions. AWR now makes life easier for circuit designers with the introduction of Analyst, a full featured, 3D EM fi nite element method (FEM) simulator. The key advantage of Analyst over other available 3D simulators is its tight integration within the Microwave Offi ce® design environment, AWR’s circuit design and simulation platform. This application note highlights the unique features of Analyst by demonstrating the optimization of the transition from a board-to- -chip signal path. The example shows how the ability to access Analyst from within in the Microwave Offi ce environment saves designers time and provides ready access to powerful layout and simulation tools that are not available in typical circuit design tools. AWR Corporation
AWR's Support of Polyharmonic
Linear and nonlinear device models are the building blocks of most RF and microwave designs. S-parameters are often used to represent linear devices. As a “black-box” model, they can easily be obtained using a vector network analyzer and distributed for simulation. S-parameters use superposition to equate the linear relationship between incident and refl ected waves at all of the device’s ports. Nonlinear devices, however, distort waveforms such that their behavior cannot be represented through superposition or S-parameters. AWR Corporation
Synthesizing & Optimizing
Like all RF and microwave components, a distributed filter design will remain only a simulation exercise if it is not created with its manufacturing process in mind. That is, the tight dimensional tolerances required to meet a set of performance goals must be within the capabilities of the filter’s manufacturing process in order to realize a reliable, repeatable filer AWR Corporation
End-to-end Design and
The X-band frequency range has been designated for critical military and public safety applications such as satellite communications, radar, terrestrial communications and networking, and space communications. It is important to ensure that these signals deliver quality, reliable, and secure communications. This application note describes the design and realization of a complex X-band transmission analyzer for use in real-time material testing. AWR Corporation
Leverage Circuit Envelope
Moving to next-generation cellular systems requires new levels of performance from RF power amplifiers (PAs). While designing PAs has always included the challenge of maximizing efficiency while delivering high linearity, never have the tradeoffs been so difficult as they are for 4G/LTE. For instance, the latest higher-order modulation schemes require exceptional linearity throughout both transmit and receive signal paths, yet wireless carriers demand the highest possible efficiency at the system level. AWR Corporation
Exactly How EM Should
Modern RF/microwave design flows make extensive use of electromagnetic (EM) analysis in many ways, and its co-existence and concurrency with circuit design and analysis can not be underestimated. Prior to the circuit design and especially in larger designs, EM tools are used to create “library” parts such as inductors, transitions, and antennas. While these parts are fairly self-contained, they must ultimately be integrated into the overall design where at the very least they must be connected to the rest of the circuit or in a more complex case be coupled to it. During both early and later stages of design, designers will switch from circuit-based models to EM analysis of critical interconnects to better understand couplings and achieve greater accuracy. EM analysis is used again before the design goes to manufacturing, so that the metal in the design can be analyzed one more time to verify circuit performance alongside design rule check (DRC ), layout versus schematic (LVS), and even design for manufacturability. AWR Corporation
Understanding and Correctly
Understanding and correctly predicting cellular, radar, or satellite RF link performance early in the design cycle has become a key element in product success. The requirements of today’s complex, high performance wireless devices are driving designers to assess critical measurements—noise fi gure (NF), 1dB gain compression (P1dB), third order intermodulation distortion versus output power (IM3dBc), and signal-to-noise ratio (SNR)—long before manufacturing begins. Traditional modeling methods such as rules of thumb and spreadsheet calculations (Friis equations) give limited insight on the full performance of an RF link in next-generation wireless products. AWR Corporation
ACE - Automated Circuit
The Traditional approach to RF/MW circuit design – which is the present day foundation for high-frequency wireless design applications – is being pressured simultaneously by an increase in operating frequencies / bandwidth and a decrease in physical footprint size. The result is that the physical design challenges faced by circuit designers are rapidly increasing, while choices for how these challenges should be best-addressed are not. AWR Corporation
Understanding Available
RF system-in-package (SiP) and multi-chip-module (MCM) designs present engineers with the challenge of integrating complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) for digital circuits and gallium arsenide (GaAs) or silicon germanium (SiGe) devices for RF and microwave circuits with soft-board laminates and low-temperature co-fi red ceramic (LTCC) packages. Software used to design these complex circuits must seamlessly bring together synthesis, simulation, and verifi cation solutions via a single interface in order to ensure optimum component design and placement in each technology. It must also construct schematics and perform physical design entry for any technology in the SiP using uniform commands and menu options. AWR Corporation
The Advantages of Multi-rate
Harmonic balance (HB) analysis is a method used to calculate the nonlinear, steady-state frequency response of electrical circuits. It is extremely well-suited for designs in which transient simulation methods prove acceptable, such as dispersive transmission lines in which circuit time constants are large compared to the period of the simulation frequency, as well as for circuits that have a large number of reactive components. In particular, harmonic balance analysis works extremely well for microwave circuits that are excited with sinusoidal signals, such as mixers and power amplifiers. AWR Corporation
Design of a Near Field
Near field communication (NFC) is being developed as a form of contactless communication between wireless devices like smartphones and tablets. This technology enables users to do things like swipe their devices at the checkout stand or wave them over another NFC-compatible device to share information instantly without complicated setups or physical connections. AWR Corporation
Steady State and Transient
Thermal effects in electronic devices are studied to investigate their influence on reliability and electrical performance. Due to the decreasing size of semiconductor devices operating at unchanged power levels, thermal analyses provide circuit designers with important information about device degradation and electro-thermal coupling. Steady state thermal analyses have been performed for many years in electronics reliability engineering to evaluate device lifetimes. Device channel temperature is the most critical parameter to determine in such a reliability study as it is the primary source for thermal degradation mechanisms. Many techniques exist for modeling and measuring device channel temperatures, however large discrepancies are reported in the literature [1]. AWR Corporation
Upfront RF Planning Speeds
High-frequency technology didn’t earn its reputation as black magic for no reason. Unlike low-frequency circuits, microwave circuits don’t behave in a totally predictable way, so “tweaking” has been an accepted mainstay of the microwave design approach/fl ow. Fortunately, high-frequency design tools have dramatically improved so that tweaking of prototype circuits is much less common, and today’s engineer has powerful tools that can make sense of the black magic. AWR Corporation
Visual System Simulator
Achieving the highest possible performance from circuits used in third-and fourth-generation wireless systems is driving a tighter integration of previously disparate tools. Certainly, a level of software synergy is essential when designing circuits for use in today’s wireless systems that employ higher-order modulation techniques together with advanced technologies, such as Orthogonal Frequency Division Multiplexing (OFDM), multiple-input multiple-output (MIMO) and digital predistortion (DPD) circuits, to name a few. As this white paper illustrates, AWR’s Visual System Simulator (VSS) and National Instruments’ LabVieW graphical programming nvironment are now co-simulating so as to better enable designers to analyze, optimize, and verify complex RF circuits, subsystems and digital signal processing within a unified framework. AWR Corporation
How to Optimize an LTE
Long Term Evolution (LTE) is rapidly being deployed by major US carriers and will serve most, if not all, top-tier markets some time during 2012. LTE is often called a fourth-generation (4G) standard, and provides signifi cantly increased peak data rates, with the potential for 100 Mbps downstream and 30 Mbps upstream, reduced latency, scalable bandwidth capacity, and backwards compatibility with existing Global System for Mobile Communications (GSM) and Universal Mobile Telecommunications System (UMTS) technology. AWR Corporation
Improved Circuit Design
To fi ne-tune an RF/microwave design to meet new design criteria, engineers turn to the built-in optimizers within their electronic design automation (EDA) software. A typical optimization case for a microwave filter, for instance, might include goals for in-band insertion loss and return loss, cutoff frequency, and out-of-band rejection. The large number of criteria that the optimization engine then has to take into consideration to create a landscape of “solutions” are more or less random, and, more often than not, quite large. AWR Corporation
Hardware in the Loop:
When simulating a complete subsystem such as a wireless communication device or radar receiver, the quality of measurement data becomes essential to ensure that the fi nished product meets or exceeds the demands the system will encounter in service. The measurement data can be used to make changes to the system early in the design process, when those changes can be realized in the least amount of time and at the lowest cost. However, this can be accomplished only if there is a direct link between the system being simulated and the measurement equipment itself—that is, when there is “hardware in the loop.”AWR’s Visual System Simulator™ (VSS) combined with its TestWave™ software provides an end-to-end communications system simulation environment that makes this possible. AWR Corporation
Using LabVIEW in the
Many veteran designers no doubt remember how comparatively simple it was to design base station or mobile phone amplifi ers when the only modulation technique was analog and amplifi er performance could be verifi ed using Additive White Gaussian Noise (AWGN). Nowadays, second (and subsequent) generations of wireless networks usher in digital modulation techniques that necessitate the need to stimulate amplifi ers and other circuits with waveforms they actually process in service. It therefore necessitates far tighter integration between the baseband signal processing and high-frequency circuit design tools as well as actual test equipment for both generating these modulated waveforms and evaluating their effects on the performance of the design. AWR Corporation
Matching Network for
One of the most common tasks required of an RF engineer is basic impedance matching. AWR’s Microwave Office® software has included this ability for a long time now via a manual ‘step through’ matching process, however, the latest release of AWR’s Microwave Office now supports the addition of an automated impedance matching wizard, coined iMatch, that allows the user to quickly compare different matching topologies and choose the best solution based upon requirements. AWR Corporation
Using Visual System Simulator
The concept of software defined radio (SDR) has existed for many years. Consequently, you can find many descriptions of an SDR. A concise definition of an SDR is a radio in which some or all of the physical layer functions are software-defined. The physical layer function is the layer within the wireless protocol in which processing of RF, IF, or baseband signals (including channel coding) occurs. Many of today’s SDRs have part of the signal processing implemented in software. AWR Corporation
Integration of Signal
The system supports easy design in cooperation with test and simulation processes using a signal analyzer/vector signal generator, as well as effective optimization of RF components and overall system performance. Using simulation based on actual measurement data reduces the amount of design and prototyping work, cutting R&D time and costs. Moreover, it can help match performance to requirements, preventing over-specification waste and cutting product costs. AWR Corporation
End-To-End System Design:
Architectural tools used by designers of RF and microwave communications systems include budget simulators, spur searching utilities, and frequency planning tools, all of which are often based on spreadsheets or hard-coded algorithms with a non-commercial user interface. Having served designers well, these “home brew” approaches are limited in functionality and/or breadth, unsupported, and are as varied as the designers who create them. While the level of effort to create these tools was great and once acceptable (if only because there was no suitable alternative), few designers today have the time required to build their own design utilities nor massage existing legacy ones to meet growing requirements of today’s communciation systems. This white paper outlines the benefi ts of using a commercial, specialized software program, such as AWR’s Visual System Simulator™ (VSS) software for end-to-end system design, while also embracing legacy approaches with the incorporation of spreadsheet views. AWR Corporation
Challenges in Verification
Emerging systems have three dimensions of complexity when it comes to making them CDC-safe. First, the number of asynchronous clock domains in designs can range from the tens to the hundreds for complex systems with many components. Second, the master clock frequencies vary per component. It is not uncommon for the ratio between the fastest and the slowest clocks to be greater than 10. Third, the clock frequencies themselves can change dynamically during the course of chip operation to save power. As a result, CDC verification becomes critical to ensure that metastability is not introduced in the design.

This article provides several situations with varying set of examples that showcase the challenges in CDC verification.
Real Intent, Inc.
TCAD Tools
TCAD Tools N/A
Reduce Verification Complexity
Verification requirements are growing in all market segments. Ensuring these requirements are met requires design verification that goes beyond traditional design rule checking (DRC), layout vs. schematic (LVS) comparison, and electrical rule checking (ERC). Small and large process nodes alike are affected by these requirements, while both system-on-chip (SoC) and full custom designs also need comprehensive reliability coverage.
Learn how Calibre PERC can help you:
  • Understand the interactions between different power domains
  • Ensure signals and voltage domains are protected for all operating conditions
  • Get easy-to-use, unambiguous debug results without exhaustive test vectors
Mentor Graphics
Micro-Cap V
The Micro-Cap V demo is a limited but working version of the main program, an easy to use mixed-mode analog/digital simulator with an integrated schematic editor. Spectrum Software
Voyeur is a visualization tool that displays a circuit schematic on the screen. N/A
BSIM3v3 code and documentation University of California, Berkeley
Power Optimization and
Power Optimization and Synthesis Environment N/A
Sunsite's /pub/Linux/apps/circuits
Sunsite's /pub/Linux/apps/circuits directory Sunsite
A simple yet powerful layout language, BALLISTIC, has been created: high-level layout code can be written for designing automated opamp generators, standard cell layout generators, and other analog integrated circuits.
Nemesis generates tests for stuck-at and bridgeIDDQ faults in combinational circuits, and simulates tests for stuck-at, bridge, and bridgeIDDQ faults in both combinational and sequential circuits. N/A
Verification IP
VIP Synopsys Inc.
Introduction to TimingDesigner
TimingDesigner Movie
(note this movie is 23 minutes long)
EMA Design Automation
HES-7 ASIC Prototyping
Co-authored by: Slawek Grabowski and Zibi Zalewski, Aldec, Inc. & Kirk Saban, Xilinx, Inc.

This paper highlights possibilities of ASIC verification using FPGA-based prototyping, considering the latest Virtex®-7 devices and Aldec HES-7 dual Virtex-7 2000T FPGA ASIC prototyping board. In addition, the most common partitioning issues and resolutions are described.
Carafe is the second generation IFA software designed to explicitly extract the bridge, break, gate oxide short (GOS), and transistor gate bridge/break faults that may be caused by spot defects using the layout of the circuit and given defect parameters. Regents of the University of California
SpyGlass Flow for XILINX FPGA
SpyGlass Lint and CDC are critical analysis tools for RTL designs that identify chip killer problems and shorten design cycle time. This document highlights the issues that come up when taking a XILINX FPGA-based design through the default SpyGlass flow. With a script-ware based approach, the work required to make the design SpyGlass compatible is significantly reduced. The approach takes care of handling Xilinx library files, design files and design constraints. Atrenta
Mastering the Magic of
Multi-patterning technology was introduced at the 20 nm node to overcome lithographic limitations in current IC manufacturing processes. While processes like double and triple patterning may sometimes seem like magic, successfully implementing multi-patterning compliance in the IC design and verification flow requires a thorough understanding of multi-patterning techniques and their impact on your design. Learn what multi-patterning is, why you need it, and how Calibre® Multi-Patterning software can help you effectively and efficiently incorporate multi-patterning into your leading-edge designs. Mentor Graphics
X-Propagation Woes: Masking
This paper presents a complete and practical methodology to comprehensively solve the X problem in RTL design. It begins by reviewing common sources of Xs, and describes how they cause functional bugs as well as unwarranted debug that prolong verification cycles. Solving the X problem helps minimize simulation and synthesis iterations and enables various design analyses (e.g. power analysis), normally performed on netlists, to begin sooner. The pros and cons of various point solutions to this problem are described. The technologies discussed include structural analysis, formal analysis, coding for X-accuracy, and simulation techniques such as random seeding of state initial values. It is essential that a complete solution address both X-optimism and X-pessimism woes as well as be applicable to all sources of Xs, facilitate debug, provide coverage analysis, and enable automation, high performance, and usability. The requirements of a complete and practical solution, based on feedback from users who deal with X issues are provided. The summary of our interaction with users is that the X problem is multi-dimensional and needs a holistic solution that brings to bear the combination of structural analysis, simulation and formal analysis to solve effectively. We describe our user experiences and a case study based on our proposed solution. Real Intent, Inc.
BAE Systems - Analog
Analog Office software and PDK support BAE System’s revolutionary mixed-signal photonics chip design AWR Corporation
Improving Design Reliability
With the advent of more complex design requirements and greater variability in operating environments, electrical overstress (EOS) is one of the leading causes of IC failures across all semiconductor manufacturers, and is responsible for the vast majority of device failures and product returns. Learn how Calibre PERC can help you:
  • Understand voltages at the pin level without SPICE simulation
  • Avoid EOS and identify oxide-breakdown conditions
  • Improve reliability and reduce verification time
Mentor Graphics
How to Achieve Power
Power dissipation is a major concern in modern day IC design. For wireless electronic appliances, battery life is one of the major influencers of the purchase decision and can be an effective differentiator. Mobile phones, PDAs, digital cameras and personal MP3 players are increasingly being sold on the long battery lives Atrenta, Inc.
QuickField 5.9
new release TeraAnalysis
Congestion Mitigation
Early physical design closure is critical for successful SoC delivery. Routing congestion is one of the key aspects of physical design closure. In this paper we have focused on the logical congestion aspects. We have established the need for a solution geared towards RTL authoring and creation teams. Some products are beginning to emerge in the EDA marketplace to tackle the congestion problem described above. SpyGlass® Physical, a new product in the Atrenta SpyGlass family, is aimed specifically toward RTL designers and offers many capabilities to resolve logical congestion issues up front, during RTL development. The product has very easy to use physical rules with debug capabilities to pin point the root cause, as well as simple reports with the congestion status of RTL blocks. Atrenta, Inc.
Atrenta SoC Realization
This White Paper deals with the way SoCs are designed, a process of substantial complexity. This design process is undergoing significant transformation, and those changes are a central part of this piece. Atrenta, Inc.
ESL anyone
This presentation and talk will present the two major approaches to ESL design entry and what is expected of the designer in each case. A specific coding example will be presented illustrating what is expecting too much of a C to RTL compiler, (and thus gets both the designer and the tool into trouble), plus the coding required to remedy the problem. Open-Silicon
Pattern Matching: Blueprints
Design patterns have a wide variety of applications in the design, verification and test flows of IC development. From significantly reducing rule deck complexity to simplifying the task of avoiding known yield detractors to enhancing workflows such as design rule waiver recognition, pattern matching has become a useful tool throughout design, verification, and test process. Learn how Calibre® Pattern Matching software can help you implement automated pattern capture and pattern matching in your various IC flows for maximum success at emerging process nodes. Mentor Graphics
An Automated Approach
This white paper describes a novel approach for memory built-in self test (MBIST) and repair insertion at the register transfer level (RTL). The approach is independent of BIST IP technology and works with any supplier\'s qualified ASIC design kit and BIST libraries. The methodology describes both a bottom up and a top down approach to SoC design and validation - all at the RTL stage. Application of this approach on real industrial designs indicates enhancement of design productivity and shorter cycle time for functional validation. Atrenta, Inc.
Avoiding Pitfalls While
In this white paper we will discuss various types of exceptions and describe how to avoid pitfalls using a systematic verification approach. Implementation tools such as synthesis and place and route make use of this information to better optimize the implementation and achieve better area, timing, power or routability. While timing exceptions are potent tool in the hands of implementation engineers, any mistake in specifying them can result in a chip failure.” Atrenta, Inc.
Combining Structural
Multiple, independent clocks have become a fact of life on SoCs and other complex ASICs. In extreme cases, such as in large communications processors, clock domains may number in the thousands. Clock domain crossings pose a growing challenge to chip designers Atrenta, Inc.
Assertion Based Verification (ABV) has proven to cut debug time in half and has been promoted as the technology having the most impact on reducing verification time and cost. SystemVerilog with ABV has been viewed as the evolving standard for the most complex chip designs.

In spite of the promise of ABV, wide scale use has not materialized. Assertion Based Verification is a difficult technology to implement and is perceived as marginally cost effective. If it were easy everyone would have jumped on it by now.
Zocalo Tech
Cadence PSpice Magnetic
PSpice®, an OrCAD® family product from Cadence®, provides industry-standard solutions ideal for engineers who require accurate analog and mixed-signal simulations. PSpice A/D is a full-featured, native mixed-signal simulator. The robust PSpice Advanced Analysis (AA) tools are used in conjunction with PSpice A/D to improve designs. EMA Design Automation
Semiconductor Weekly
Research Wells Fargo Reseach
Improve Reliability with
Power challenges in today's IC designs create a significant increase in verification complexity. Critical design rule checking of variable spacing rules for densely packed multi-voltage nets is often verified with the traditional use of marker layers, a tedious and error-prone technique. Without an efficient means of verifying variable spacing within nets, designers often play it safe and simply apply maximum spacing throughout specific areas of a design, wasting valuable design area. Learn how to:
  • Optimize design size with correct voltage spacing rules
  • Avoid TDDB within your designs
  • Improve reliability and free yourself from manual marker layers
Mentor Graphics
Constraints Management:
Constraints management is a major concern for designers today and increasing design complexity, coupled with mounting time to market pressure, makes faster timing closure and reduced iterations a necessity. Any late stage constraint change brings with it enormous costs, both in terms of time and money, and can lead to a failed design project Atrenta, Inc.
Analyzing Power Integrity
When a printed circuit board (PCB) includes a power plane that is near to signal traces or other power planes, there is a significant risk of energy transfer between parts of the system. Not only does this coupling lead to power switching noise being transferred into data signals, it also means that power supply systems may demonstrate additional resonances that are not seen in the individual components. This can affect the power integrity of the PCB and may reduce its speed or reliability. This paper will explore some of the potential power integrity issues that can affect a PCB and explain how simulation can be used to help reduce these effects. CST-Computer Simulation Technology
Semiconductor Weekly
Research Wells Fargo Reseach
Altera video
video Altera Corp.
Well Fargo Research:
Research Wells Fargo
Modeling and Verifying
This paper describes a novel method for modeling and verifying cache-coherent protocols using Jasper ActiveModel™ technology. The methodology and benefits of using ActiveModel technology to model and verify the ARM AMBA® AXI Coherency Extensions (ACE™) protocol are outlined. In addition, it describes how an ActiveModel protocol model becomes a valuable piece of system-level verification intellectual property (VIP) used to verify RTL designs. Finally, the collaboration between ARM and Jasper that resulted in the development of the interface-level VIP needed to verify RTL designs supporting the ACE protocol are detailed. Jasper Design Automation
Automated Assembly and
Platform-based methodology is projected to become the dominant approach for SoC design in the very near future. Automated assembly techniques equally will become the standard approach for building these designs in order to manage complexity, time to market and development cost. Adopting such techniques can have significant impact on each of these factors and carries a significantly lower startup cost than many people assume. More importantly, these techniques are starting to become a competitive advantage, especially in consumer segments. In this White Paper, we have reviewed the key steps needed to implement automated assembly methods. We have reviewed the costs and benefits associated with these tasks and discussed how they are working today for real designs. Atrenta, Inc.
Great Connections for
I am struck at how easy it is to get used to “good enough” ways of working. Often we fail to notice new innovations that can make our tasks easier and boost our productivity and reduce risk to success. When asked about connecting to other design team members locally and worldwide, engineers might think of a VPN link to their office computer or the headquarters email server. However, they would be missing the exciting developments of a whole new way of working that brings collaborative resources to bear on the design process, so that design creation, verification and integration is easier and less costly to do.
Die Level Process Monitors
In the silicon debug process, the basic question needs to be answered; do I have a process problem or a design problem? Unlike conventional ring oscillator based, scribe line based structures, Ridgetop's patented approach provides fabless semiconductor firms with effective tools to help accelerate silicon debug. Ridgetop's proven die level test structures allow more precise monitoring and troubleshooting for advanced IC design. Self-contained and occupying minimal space, the structures can be used to measure critical mismatch parameters and the extent of NBTI effects (intermittencies). Ridgetop Group, Inc.
UVM Reference Flow Overview
An overview of the UVM Reference Flow community contribution from Cadence. Presentation reviews what is the UVM Reference Flow contents, discusses roadmap and legal considerations, along with other facts needed for users looking to have a standardized reference for the UVM. Cadence Design Systems, Inc.
Clock Concurrent Optimization:
Timing divergence has a critical impact on the economic viability of migrating to sub-65nm process nodes. Clock concurrent optimization (CCOpt) is a revolutionary new approach to timing optimization: it merges physical optimization into clock tree synthesis and simultaneously optimizes clock delay and logic delay using a single unified cost metric. With CCOpt technology, engineers can achieve timing convergence and have a new degree of freedom to design and integrate faster, smaller, lower-power digital chips. Cadence
Analysis of Random Resistive
Traditional netlist-based DFT analysis runs into design rule violations during scan insertion in synthesis and needs RTL designers to modify the design for uncontrollable clocks and resets. Similarly, low fault coverage during ATPG results in designers having to modify RTL to improve observability and controllability causing many design iterations and schedule impact. Atrenta
Reduce Power, Area and
This paper, using an example design, demonstrates how to meet challenging performance, latency and bandwidth goals by using the DesignWare® Interconnect Fabric for the ARM® AMBA® 3 AXI™ while minimizing the total area, power consumption and number of top-level wires. The paper also studies the design requirements and examines the optimization features of the DesignWare Interconnect Fabric used to meet the stringent timing requirements. Detailed technical analysis is provided for the selected architecture, pipelining mode, arbitration scheme and the slave visibility feature employed to reach timing closure for the links with demanding performance requirements. Final results are presented based on the hybrid architecture of the DesignWare Interconnect Fabric used to optimize the infrastructure resulting in a reduction in area, power and routing congestion. Synopsys Inc.
Facilitating At-speed
This white paper demonstrates a solution for facilitating at-speed test at the register-transfer level. The RTL approach is important, because designers and test engineers usually verify the test coverage only at the gate level during the final ATPG stage. This RTL solution thus saves weeks of effort by fixing potential issues up front. Atrenta, Inc.
Semiconductor Weekly
Report Wells Fargo Reseach
Semiconductor Weekly, Dec. 6
Industry Analysis Wells Fargo Reseach
Get IEEE 1685™ Launches
The IEEE announced today the launch of Get IEEE 1685™, a website where users can download the current version of the standard free of charge. Acellera
Semiconductor Weekly Dec. 20
Research Wells Fargo Reseach
Cadence EDA360 Vision Paper
Today, systems and semiconductor companies are undergoing a disruptive transformation so profound that even the best-known companies will be impacted. The EDA industry now stands at a crossroads where it also must change in order to continue as a successful, independent business. The disruptive transformation we are speaking of is not about EDA developing new design tools. It is not about new methodologies. It is not about the functional verification crisis, or the move to electronic system level (ESL) design, or any of the issues that have dominated discussions about EDA to date. It is about something much larger. It begins with a shift from design creation to integration in the electronic systems industry, and results in a new focus on profitability. This realization, in turn, opens the way to EDA 360, a new vision for what the EDA industry can become. Cadence Design Systems, Inc.
Requirements for Soft
This white paper focuses on how SoC designers and integrators can effectively assess the quality and completeness of soft IP cores. A methodology for accomplishing this goal is presented, and an overview is provided of the Atrenta IP Kit - an application of the SpyGlass® platform that implements a soft IP quality qualification methodology. Atrenta, Inc.
Dynamic Design Analysis
Static analysis tools provide many types of insight into the design and are being widely used to detect and prevent various potential problems with designs. Applied during various phases of the design project, they can detect minor issues to the most serious errors in designs. Tools in this category include Design Rule Checking (DRC), Clock Domain Analysis, Automatic Formal Verification and Formal Verification Tools. AXIOM Design Automation
An overview - Aizyc Technology
Aizyc Technology is a semiconductor design services and SoC IP company. Available IP Cores - SDIO 3.0 Host & Device, USB 2.0 IP, Ethernet IP + TOE, MIPI SLIMBUS. Services include Chip Design, Silicon Validation, Physical Design, Firmware & Embedded systems development. Aizyc Technology
Analyzing RF Coexistence
A typical smartphone handset can contain numerous different RF systems, including multi-band cellular antennas, Wi-Fi, Bluetooth, NFC and navigation systems such as GPS and GLONASS. All these systems need to be able to coexist without causing cosite interference. This application note shows how CST STUDIO SUITE® and Delcross EMIT can be used to investigate interference between antennas on a smartphone, and how potential mitigation strategies can be investigated using simulation. CST - Computer Simulation Technology
Corporate and Product Overview
Real Intent is the leading provider of EDA software to accelerate Early Functional Verification and Advanced Sign-off of digital designs. It provides comprehensive clock-domain crossing verification, advanced RTL analysis and sign-off solutions to eliminate complex failure modes of SoCs. The Meridian and Ascent product families lead the market in performance, capacity, accuracy and completeness. Real Intent, Inc.
High Performance Computing
CST - Computer Simulation Technology
Making Floating-Point
Floating-point arithmetic becomes a widely used format in digital system design. For example, DSP applications often demand high precision while operating with large dynamic ranges. The IEEE 754™-2008 floating-point arithmetic standard fulfills this criterion but it might be extremely hard to comprehend and use. This document discusses challenges associated with debugging floating-point arithmetic designs and explains how to tackle them using the tools available with your floating-point aware IDE. Aldec, Inc.
How A Call For SOS Improved
Milandr, a 15-year-old product company based in Moscow that builds high-reliability integrated circuit (IC) products for the aerospace, avionics, automotive, and consumer markets, discusses the use of Cadence Virtuoso and ClioSoft SOS to reduce cycle time and improve designer productivity. Cliosoft, Inc.
Cadence Allegro Design
PCB designers who require state-of-the-art functionality, performance and productivity have always relied on Cadence® Allegro® PCB Design products. Whether it’s the unique real-time, embedded, shape-based routing engine that optimizes the router or the constraint-driven, interactive floorplanning methodology for placing components—the Allegro suite of PCB tools provides you with the most comprehensive and cost- effective design solution that is available today. In this webinar, we’ll demonstrate how you can take a project from inception in design capture, the addition of constraints, through placement and routing, all the way to manufacturing output—without leaving your design environment. You can achieve all of this by using Cadence Allegro Design Entry CIS and Cadence Allegro PCB Editor. EMA Design Automation
Active-HDL 8.2
Active-HDL is an integrated easy-to-use FPGA Design and Simulation solution, providing a robust design creation tool suite, a high-performance mixed-language simulator and a multi-vendor FPGA flow manager that controls Simulation, Synthesis and Implementation for industry leading FPGA devices, such as Actel™, Altera®, Lattice®, Quicklogic®, Xilinx® and over 87 popular EDA tools, all-in-one common environment. ASICSoft, Inc.
Ensuring the hardware testing results match RTL simulation results is the key to the strict verification guidelines of DO-254. This paper describes how to replay RTL simulation environment in the real hardware with the same flexibility, traceability and coverage ideal for DO-254 certification. Aldec
Ways of Bypassing CPU
Direct Memory Access (DMA) is one of several methods for coordinating the timing of data transfers between an input/output (I/O) device and the core processing unit or memory in a computer. DMA is one of the faster types of synchronization mechanisms, generally providing significant improvement over interrupts, in terms of both latency and throughput. An I/O device often operates at a much slower speed than the core. DMA allows the I/O device to access the memory directly, without using the core. DMA can lead to a signifi-cant improvement in performance because data movement is one of the most common operations performed in processing applications. There are several advantages of using DMA, rather than the one in which core does a memory to transfer operation and vice versa and this paper discuss all these advantages with various applications of DMA Controller. DMA is used in almost every complex system or subsystems , but its observed that teams either build the DMA controller from scratch for each project for specific application or take the existing DMAC available from elsewhere. Here in this article I have tried to discuss the architecture of DMAC that can be used with any kind of Bus, configuration (parallel, serial transfers), can be connected to any kind of ports, most importantly any kind of software assumptions can be implemented in the DMAC very easily. I call it Universal DMA Controller. MindTree Ltd
Reducing Verification
Precise verification coverage measurement remains a significant IC development requirement. By combining the exhaustive nature of formal technologies with accurate Observation Coverage techniques, OneSpin has moved the state-of-the-art forward in this critical area. Download this whitepaper to learn more about the Observation Coverage approach and how this has been leveraged in OneSpin's new Quantify coverage technology for precise, rapid formal and simulation coverage assessment. OneSpin Solutions
Is it time to switch
Six years ago, when OASIS was introduced, we published an article highlighting why it was a positive replacement for GDSII [1]. Since then, users have started adopting OASIS in their flows, with benefits and disadvantages. One of OASIS strengths is its flexibility (unlimited coordinate precision, unlimited number of layers, etc...). But this flexibility has a price in terms of memory consumption and computing time. A new standard, OASIS.MASK, is being introduced to address the requirements specific to photomask layout repre- sentation. This subset of OASIS (and as such fully OASIS compliant)introduces constraints that reflect the real-world limitations of mask manufacturing. As a result, OASIS.MASK interpretation and exploitation is more efficient and reliable. [1]P. Morey. Going from gdsii to oasis. EEtimes, December 2008. Xyalis
Lessons in developing
Using external VIP (Verification IP) brings several advantages including availability, independence in both checkers and coverage, robustness from use in several environments. However, the VIP must be developed so that it is easy for the user to incorporate the VIP into their environment. In this paper we look at practical lessons learned in both the development and deployment of VIP for use in complex OVM (Open Verification Methodology) SoC (System-on-Chip) verification environments. Test and Verification Solutions
The ROI of Hardware Configuration
Software teams have long realized the return on investment (ROI) of software configuration management (SCM) systems, which have been used by software teams for decades to manage development, improve collaboration, and coordinate releases. In fact, SCM systems have become such an integral part of a software development environment that practically no significant software project is even started without a SCM methodology in place. Over the last decade, hardware design teams have encountered the same market forces as software designers: increased competition due to globalization, mandating the use of the best available engineers irrespective of location; an exponential increase in design complexity; and shrinking market windows. The result has been larger teams of engineers spread across multiple sites, managing complex flows, and sharing a large volume of constantly changing data. They need hardware configuration management (HCM) systems. Cliosoft, Inc.
The Concurrent design
Am interesting experiment run in DAC this year to show benefits and drawbacks of different teams working in parallel. Duolog Technologies
Safety Weapon Interlock
SWISS is designed for defense to provide necessary interlock signals to the Ship’s weapon control systems for permitting and prohibiting firing of weapons. It ensures safety of ship, onboard men and machine from possible mid air collision of fired ammunition, close to the ship. Dexcel Electronics Designs Pvt. Ltd.
Designing with Cadence
Cadence® OrCAD® Capture offers a comprehensive solution for entering, modifying, and verifying complex system designs quickly and cost-effectively. Whether used to design a new analog circuit, revise a schematic diagram for an existing PCB, or design a digital block diagram with an HDL module, OrCAD Capture allows designers to enter, modify, and verify the PCB design. EMA Design Automation
PCB Design Fundamentals
Designing a printed circuit board (PCB) can be quite a challenge when you don’t understand the capabilities of your design tools. Creating designs with critical requirements and narrow deadlines requires engineers to have comprehensive knowledge of the CAD tool you use daily. Even understanding some of the fundamental operations like importing / exporting mechanical CAD data, creating a PCB library of footprints, physical constraints management etc., can save time and make your job easier and more productive. EMA Design Automation
A New Method to Improve
Tomorrow's memory standards hold the promise of higher performance. With the uncertain future of which protocols will emerge as industry standards many system architects conservatively choose from current DDR standards - adopting a "wait and see" approach. However, the needs to improve system performance and reduce power consumption are still paramount with next generation products. With memory subsystems representing significant influences on these two areas, designers must find new methods to improve the performance of memory sub-systems. The Performance-IP method discussed here is implemented using small, distributed, logic elements requires no code changes and does not require the increase of system clock rates. Performance-IP LLC
New Approach to Accelerating
Despite many efforts to automate analog design and layout, these tasks remain primarily a full custom process, ; with the result that analog is occupying a larger and larger portion of the total design cycle time. Efforts to automate analog design have not been successful in the marketplace because the tools have not been able to equal the quality levels of full custom design, are complex to set up and use, and are expensive. Tanner EDA’s new tool forgoes full automation in favor of accelerating the layout process by generating key analog design primitives, such as current mirrors and differential pairs. These primitives are often the most time-consuming aspect of layout and indeed the parts that are critical to the functionality of the silicon. The new tool applies matching techniques to address common processing artifacts, produces the optimal solution for parasitics and silicon area, and creates devices optimized for high yield. Tanner EDA
Matching Circuit Optimization
Impedance matching is an essential part of antenna design. The input impedance of an antenna needs to be reasonably close to the amplifier impedance (e.g. 50 Ohm), otherwise the signal is reflected back to the amplifier and not radiated by the antenna. In many applications matching circuits consisting of discrete inductors and capacitors, or transmission lines are used to improve the impedance matching characteristics of the antenna. This white paper discusses the optimization of matching circuits especially to antenna applications. Although the design of matching circuits sounds simple, there are many practical considerations that need to be addressed. CST - Computer Simulation Technology
Design and Verification
We propose a new methodology flow which will allow the visual definition of a complex SoC through instantiation of parametric IP such as processors, SDRAM controllers, DMA engines, on-chip buses, peripherals, switch matrices and coherency directories, coprocessors, etc. Script based automation helps in integrating any IP with any configurations ,selects relevant and corresponding Verification IPs(in-house developed-if Design IPs are standard), uses suitable Bus Wrappers(OCP,EBI,Avalon,MicroBlaze,PicoBlaze,PIF,AXI,AHB,APB,Generic and others) and stitches all the components design as well verification(synthesizable testbench components ) together and making use of TLMs,BFM (replacing CPUs with Master BFMs) or Process Core based designs creates an CSOC environment. The framework reduces the time to build integration and verify the functionality-it also has the complete set up from assembler to DFT. MindTree Ltd
Enhanced Design Reuse,
Designers reduce board layout and placement time from weeks to minutes through CircuitSpace® AutoClustering™ technology, intelligent design (IP) reuse, and replication. Reductions in PCB design time have a direct impact on time-to-market for new products, which directly correlates to profitability. EMA Design Automation
New Approach to Accelerating
Despite many efforts to automate analog design and layout, these tasks remain primarily a full custom process, ; with the result that analog is occupying a larger and larger portion of the total design cycle time. Efforts to automate analog design have not been successful in the marketplace because the tools have not been able to equal the quality levels of full custom design, are complex to set up and use, and are expensive. Tanner EDA’s new tool forgoes full automation in favor of accelerating the layout process by generating key analog design primitives, such as current mirrors and differential pairs. These primitives are often the most time-consuming aspect of layout and indeed the parts that are critical to the functionality of the silicon. The new tool applies matching techniques to address common processing artifacts, produces the optimal solution for parasitics and silicon area, and creates devices optimized for high yield. This paper outlines explains how. Tanner EDA
DesignWare SATA AHCI
This application note describes how to configure and connect the DesignWare® SATA AHCI IP core to the Synopsys PHY in a multi-port AHB-based configuration, and provides an analysis of the expected throughput on each port based on assumed system parameters. The expectation is that a user should be able to take this example and insert actual system parameters to come up with a performance estimate. We will look briefly at the architecture of the core to enable a better understanding of the subsequent sections describing the configuration and performance calculations of the core. Also, note that while this document only discusses the performance of an AHB-based configuration, the option to select an AXI-based configuration will be available in the near future. Due to the nature of the AXI-bus, which allows for overlapping transfers, we expect an increase in the performance of a multi-port configuration. Synopsys Inc.
Invarian Addresses Sign-Off
IC designers responsible for the physical implementation of the design face a huge problem of design sign-off analysis. Today, they need to use different tools to verify the various design aspects, such as timing, power, voltage drops, and chip temperature. The problem is that each of these analyses needs the results of all the other analyses. Therefore, typically, these tools are run sequentially in a flow, so that the results of one tool can feed the next tool. Invarian
Fundamentals of NAND
This white paper presents very important information for managers, engineers, and system architects who are working with NAND Flash memory. Eureka technology
Facilitating Unreachable
Code coverage is a popular method to find design bugs and verification loopholes. However, once a piece of code is determined to be unreachable, diagnosing the cause of the problem can be challenging: since the code is unreachable, no counterexample can be returned for debugging. Therefore, engineers need to analyze the legality of nonexistent execution paths, which can be difficult. To address such a problem, we analyzed the cause of unreachability in several industrial designs and proposed a diagnosis technique that can explain the cause of unreachability. In addition, our method provides suggestions on how to solve the unreachability problem, which can further facilitate debugging. Our experimental results show that this technique can greatly reduce an engineer’s effort in analyzing unreachable code. Avery Design Systems, Inc
Timing efficient cell
Pin multiplexing is a common practice applied in order to save large number of pads in an SoC. This reduces the Die area of the chip but impose a number of limitations, like requirement of dedicated, complex pin muxing circuit. Traditionally there are three major types of pin multiplexing circuits which are in use; arbiter based , resgister configurable and priority muxing . Out of these , priority muxing simplifies the muxing strategy as it muxes the various functions together on the basis of timing criticality , also it utilizes the IP’s in built select signal . In this paper we propose a novel MUX cell design which can be applied at the places where priority muxing is used. This muxing strategy enables muxing of functions with equal timing criticality together at one single pad even with the priority intact. Which in turn limits the number of high driving pads in SoCs hence saving power and area both? The proposed circuitry is technology independent and also saves area . This circuit is applied in a SoC at 90nm technology by replacing traditional priority based pin muxing and almost 72% area saving and significant interface frequency increase is achieved Freescale Semiconductor
Whats Behind Digital
Like any new technique that is introduced in the market, digital power control must first prove that it offers important advantages over state-of-the-art analog techniques. In this vein, the first and foremost issue to be addressed is the price, and the secondary considerations are converter size, performance and efficiency. This article covers these issues and also discusses digital power control from a broad standpoint. ZMDI
Understanding and Reducing
Achieving the least possible delay in a video capture, streaming, and display system can be surprisingly affected by the specific H.264 encoder near the beginning of that flow. Read this white paper to learn more about what determines latency, and how to pick the best encoder for achieving low latency in your systems. CAST
Considerations for Bulk
A group of leading semiconductor companies have developed a roadmap for leveraging CMOS designs intended for manufacturing on bulk silicon to fabricate ICs on fully depleted silicon-on-insulator (FD-SOI) substrates with ultra-thin buried oxide layers, producing chips with improved performance and lower operating power. This white paper shows that porting circuits from bulk silicon to FD-SOI can be very direct, depending on the FD-SOI technology used by a specific chipmaker. SOI Industry Consortium
Developing robust power
Power line communications (PLC) is a global technology with worldwide interest in its development. In its simplest terms, PLC modulates communication signals over existing power lines. This paper highlights specifications for several PLC alliances and specifications and discusses new proprietary PLC technologies. Texas Instruments
Verifying Hardware and
i have been ardent fan of Toyota manufacturing.Toyota was the first company who streamlined the processes and quality matrix in the factory units , established a flow and performance management in for the workers and implemented a methodology to track the production.This was indeed very different from the Ford(American) and other European companies who till then have been very much stressing on the luxury ,customization etc etc.. MindTree Ltd
Cadence OrCAD Layout
Cadence® has begun the End-of-Life process for Cadence OrCAD® Layout technology based products EMA Design Automation
Managing Electrical Constraints
Cadence® Allegro® Design Entry CIS integrates a proven schematic-design-entry system with a robust component information system (CIS). Whether used to design a new analog circuit, revise a schematic diagram for an existing PCB, or design a digital block diagram with an HDL module, Allegro Design Entry CIS allows designers to enter, modify, and verify the PCB design. It also promotes reuse of preferred components and known good-part data. EMA Design Automation
Assertions are properties or facts describing the required and forbidden behavior of a design. They are “executable specifications” that are monitored during simulation by assertion checkers included in the design file. Zocalo Tech
Continuous Glucose Measurement
ASIC development by ZMDI of an implant for continuous glucose measurement. Whitepaper published in MEDIZEN+elektronik Magazine (01/2013) ZMDI
Bluetooth 3.0 + HS - Features
This presentation/whitepaper is targeted for developers who already have an understanding of the Bluetooth technology and who would like to get a quick understanding of the new features introduced in Bluetooth 3.0 + High Speed version of Bluetooth Specification. Wipro Technologies
Power Architecture evaluation
Cosmic tools for Power Architecure family, evaluation version limited to 8k. Cosmic Software
Finding Reset Nondeterminism
Due to increases in design complexity, routing a reset signal to all registers is becoming more difficult. One way to solve this problem is to reset only certain registers and rely on a software initialization sequence to reset other registers. This approach, however, may allow unknown values (also called Xvalues) in uninitialized registers to leak to other registers, leaving the design in a nondeterministic state. Although logic simulation can find some X-problems, it is not accurate and may miss bugs. A recent approach based on symbolic simulation can handle Xs accurately; however, it is not scalable. In this work we analyze the characteristics of X-problems and propose a methodology that leverages the accuracy of formal X-analysis and can scale to large designs. This is achieved by our novel partitioning techniques and the intelligent use of waveforms as stimulus. We applied our methodology to an industrial design and successfully identified several Xs unknown to the designers, including three real bugs, demonstrating the effectiveness of our approach. Avery Design Systems, Inc
Derating of Schottky Diodes
Schottky diodes use a metal-semiconductor junction as opposed to the semiconductor-semiconductor junctions used in standard diodes. This configuration allows for lower forward bias voltage drops (0.15V - 0.45V vs. 0.5-0.7V) and faster switching times, making them ideal for power supply switching operations. Drawbacks for schottky diodes include much higher reverse bias leakage current ratings. Because p-n recombination is not a factor in switching delay time, only capacitance affects the reverse switching time. DfR Solutions
Verification of H.264
H.264 high and baseline profile codec systems are implemented on Virtex-5 multi- FPGA board. The codec supports full HD class video and the FPGA board called iNEXT consists of up to four 33-million FPGA. Dynalith
SI/PI and EMC/EMI Simulation
CST PCB STUDIO™ is a specialist tool for the investigation of Signal and Power Integrity and the simulation of EMC and EMI effects on PCBs. Regardless of the application type – high speed digital, analog/mixed signal, or power supply – CST PCB STUDIO (CST PCBS) will help you to get it right first time. CST - Computer Simulation Technology
Show Me Next-Generation HDMI
With an install base of over 1.1 billion devices worldwide, HDMI has become the de facto multimedia interface for all digital home and mobile/portable multimedia devices. The recently introduced HDMI 1.4 specification further reinforces the HDMI message of performance, reliability and simplicity. Features like the HDMI Ethernet and Audio Return Channel (HEAC), introduced in version 1.4, further simplify digital home theater wiring while adding new and innovative features. In addition, the HDMI 1.4 specification supports advanced media capabilities such as enhanced color spaces for digital still cameras, 3D modes and ultra-high resolution display formats (up to 4x higher than 1080p) that will be key features in the nextgeneration of premium multimedia entertainment consumer electronic products. Synopsys Inc.
EDWin XP 1.71
EDWinXP is a Total Integrated EDA/ECAD Software package of seamlessly integrated, task oriented modules covering all stages of the electronic circuit design process - from capturing the idea of a circuit in the form of schematic diagram to generate a full set of documentation for manufacturing and assembling of PCBs". It is a complete suite that has Schematics Editor, PCB Layout Editor, Fabrication manager, Library manager and many more Visionics
Using Static Functional
This paper presents a study of verifying a memory controller using a static functional verification tool. Static functional verification is a new technology that does not use vectors or dynamic simulation but analyses the behaviors of a design by the use of a property language. This paper presents the design and verification challenges of a controller, and how static verification was used to debug the design, what improvements were seen in methodology, and what was achieved and learned by using a static tool. Averant
An Introduction To Property
The increasing complexity of system-on-a-chip and ASIC designs has caused an ever-widening gap between what can be designed and what can be. It is estimated that between 50-70% of the time required to design a complex IC is spent in verifying that the functionality of the system is correct. Bugs in a design are least expensive to fix just after they are created. At this stage the design is still fresh in the designer's mind and other parts of the project or other design team members are unaffected. Bugs are at least an order of magnitude more expensive to fix during system integration. In this phase it takes more time and people to analyse the cause, regression tests must be rerun, and the entire group may be delayed. These challenges are giving rise to some exciting new tools and approaches in Verification techniques. Averant
Solving Verilog "X" issues
Paper by Mike Turpin of ARM, Ltd., describing how to use Solidify for Sequential Equivalence check in order to uncover hidden "X" values in a design. This is particularly important for an IP provider where the RTL may be implemented using different synthesis flows. Hidden X's can cause differences between RTL simulation and the actual silicon, which are not caught by design flows that rely on other tools such as Logical Equivalence checking. Averant
A Guided Tour of SimCluster
SimCluster is an innovative parallel, distributed simulation environment that provides a scalable, open, and flexible solution to increase RTL and gate-level simulation performance and capacity by 300-700% or more. SimCluster supports Verilog and VHDL design methodologies and the most popular simulators (NCVerilog, Verilog-XL, VCS, and ModelSim), hardware accelerators, and emulators. Avery Design Systems, Inc
Complete NAND Flash Solution:
NAND FLASH memories are non-volatile, inexpensive and of high capacity. These characteristics make these devices ideal for fulfilling the storage requirements in the exploding mobile device market. Designers using NAND FLASH devices should follow the ONFI standard interface to ensure that their controller design will operate with devices from any vendor. The memories need both digital and analog interfaces between the devices and the system they serve. When designers add NAND devices to the system design they must consider the least expensive and lowest risk means of implementing the controller. Arasan Chip Systems
Designing affordable,
Texas Instruments (TI) leading power line communications (PLC) technology has enabled Cygnus Electronics to create a PLC hardware and software platform designed for automotive qualification in electric vehicles. Auto-rem implements the Society of Automotive Engineers’ (SAE) J2931-3 specification, which is a narrowband orthogonal frequency division multiplexing (OFDM) proposal for plug-in electric vehicle (PEV) to electric vehicle service equipment (EVSE) communications during PEV battery charging. Texas Instruments
The Second Life of Data:
Written by Gregg Oetting, this technical paper highlights the expectations and challenges of data translation and the importance of model repair and validation. Based on a broad suite of test results, this paper can be an invaluable tool in customer engagements to help highlight the true cost of low quality translation. Spatial
Using Plots for HDL Debugging
The most commonly used approach to analyzing objects in an HDL design, is based on the well-known digital waveforms available with any commercial simulator today. Such a time domain representation of data with respect to time, allows verifying many parameters of a designed digital system, but it may not be efficient for applications such as image processing, digital filter design, embedded system design, and others. This document presents Plot, a new solution for a graph-based analysis of HDL objects, correlations between them, and a number of practical applications for it. Aldec, Inc.
Thermal Modeling of Heat Sinks
Heat sinks transfer generated heat in an electric system away from the active and passive electronic components and toward the ambient environment. This article describes thermal management via temperature distribution and heat flow simulation using CST MPHYSICS® STUDIO. CST - Computer Simulation Technology
Mastering the development
Today’s “smart” products leverage an intelligent combination of mechanical, electrical and software to deliver capabilities that weren’t achievable before. While bringing significant benefits for customers and for the companies that produce them, they brought as well a new level of complexity to product design and development. In this Whitepaper, Tech-Clarity Research identifies the impact of "smart" products on engineering and product development and outlines a number of tangible steps using proven best practices and technology to improve mechatronics product development maturity. Dassault Systèmes
BOSCH : An integrated
"You could say the library is the brain of our development. All the information our developers need for their work is stored centrally, so they know, for instance, whether they can use a component for a new development or when it has been discontinued” Lutz Napiwotzky, responsible for Engineering Applications Corporate IT at Bosch. When the Bosch Group’s Automotive Technology Division, one of the world's leading suppliers to the automotive industry, analyzed their development processes, they quickly identified areas for improvement, including consistent data management. Each division structured data differently and stored it in different systems. As a result, tasks like tracing component use were inefficient and sometimes impossible. After implementing Dassault Systèmes’ 3DEXPERIENCE platform Bosch engineers understand exactly which components were installed in which devices, including all configuration and material information. In particular, the component library structuring and versioning capabilities bring significant value to the Stuttgart-based company. Dassault Systèmes
SuperSpeed Your SoCs
Since the introduction of the original USB standard in 1996, the USB interface has become one of the most successful connectivity standards. In today’s highly connected world, USB connections are found in the computing, consumer, mobile, industrial and automotive segments. Products are far ranging — from PCs and portable audio/video players to cell phones and digital TVs. With the trend of increasing data storage requirements driven by applications, such as high-definition video, combined with the desire to move this data quickly between host, storage, and portable devices, it was only a matter of time before there was a need to make this well-known standard even faster. This heralds the third-generation of this ubiquitous standard — the arrival of SuperSpeed USB 3.0. Synopsys Inc.
Preparing PCB Designs
Preparing a printed circuit board (PCB) design for manufacturing can often be a tedious and time-intensive task. A major trend in high-volume production designs is the use of complex powerplanes to keep layer count to a minimum and reduce the cost of manufacturing. Generating multiple types of manufacturing outputs helps widen the path to PCB manufacturing. Lastly, providing the fabrication vendor with accurate design data can directly improve product quality. EMA Design Automation
ACADto3Di is 3D modeler for IC packages that have been "drawn" inside of AutoCAD. It enables any package designer to create a 3D model from a simple bond document. Once converted to the 3Di format, the package can be viewed in 3D and the wires can have a full 3D DRC performed. Artwork Conversion Software, Inc.
New Race, New Rules,
As technology development begins to outpace manufacturing capability and price points continue to drop, semiconductor manufacturers are searching for new strategies to meet these increasing demands. Shrikrishna Gokhale, Head of Sasken’s Semiconductor Division, explains. Sasken (Formerly Silicon Automation Systems Inc.)
Think Anew Why Frequency
Old thought: “If I stop what I’m doing, I’ll be lost and will never start again.” New thought: Sometimes, we have to stop and find our path.1 E System Design Inc.
Verification Bug Metrics
  • The hardest question for a DV manager to answer
  • How does chip design use metrics today?
  • How does Software do it?
  • Adapting SW metrics principles to HW design
  • Actual project data
Sigasi 2.0 Starter Edition
Sigasi 2.0 Starter Edition is a freemium tool for VHDL design entry, code comprehension and design reuse. It is designed to make existing text editors like Emacs and VIM obsolete. Full functionality of Sigasi 2.0 Pro is available for free, for small projects. Sigasi
Mega Video Solutions
Oliver Vellacott, IndigoVision’s CEO, introduces the concept of Mega Video Solutions for CCTV surveillance and describes the key elements in their design. IndigoVision Inc.
Improving Design Time
PCB designers have relied on CircuitSpace to expedite their design process for several years. One such customer is Troy Snow, Senior PCB Designer with an Original Equipment Manufacturer (OEM) located in Austin, Texas, who has been using this software throughout his career. EMA Design Automation
Simulating Crosstalk
Cables not only transfer the power needed to run electrical equipment, but also the data signals needed to operate them. To prevent errors and device failures, the same attention must be paid to the choice and installation of the cabling as is paid to the rest of the system. CST - Computer Simulation Technology
A Multiphysics Approach
The magnetrons used in microwave ovens operate on the same frequency band as Wi-Fi equipment, and the radiation they release can interfere with the operation of wireless networks. This paper presents a multiphysics simulation of a magnetron using CST STUDIO SUITE®, with the aim of testing the electrical, magnetic, thermal and mechanical characteristics of a low-interference magnetron design. The simulation results are then compared to measurements made experimentally, and the two sets of results are shown to be in good agreement. CST - Computer Simulation Technology
GPU Computing
The high memory bandwidth and parallel processing abilities of GPU cards mean that GPU computing can provide significant simulation speed advantages over conventional CPU computing. CST STUDIO SUITE® supports GPU computing in the transient solver, integral equation solver and particle-in-cell (PIC) solver, using NVIDIA Tesla® GPU cards. CST - Computer Simulation Technology
Electromagnetic Simulation
Electrically large structures such as aircrafts, ships, land vehicles and satellites have demanding and complex electromagnetic environments. CST STUDIO SUITE® brings together 20 years of experience in the simulation of 3D microwave & RF components, antennas and systems ... CST-Computer Simulation Technology
A Virtual Reality Camera
Blueprint for the design of a virtual reality camera recording and compressing 16 full HD (1080p) simultaneously sharing a single DDR3 DRAM chip with 16 bits data bus. Both I and P frames are used thanks to the reference frame compression with Compressed Frame Store (CFS) technology. Ocean Logic Pty Ltd
A study of AES and its
This White Paper provides some practical examples of calculating the Advanced Encryption Standard (AES) on 16 and 32-bit versions of eSi-RISC. The basic software implementation is refined using known techniques in the literature, and a novel implementation of Bertoni’s transposed MixColumns() transformation provides the most optimised fully software implementation. The final cycle count on eSi-3250 is shown to be better than ARM7TDMI, ARM9TDMI and LEON-2 embedded processor benchmarks and the code density is superior. Finally the white paper looks at how the user-defined instruction extensions can provide additional saving in power, memory and computation cycles. EnSilica Ltd
Monte Carlo Graphical
Cadence® PSpice® A/D is a full-featured analog simulator with support for digital elements to help solve virtually any design challenge—from high-frequency systems to low-power IC designs. The powerful simulation engine integrates easily with Cadence PCB schematic entry solutions, improving time to market and keeping operating costs in check. An interactive, easy-to-use graphical user interface provides complete control over the design process. Availability of resources such as models from many vendors, built-in mathematical functions, and behavioral modeling techniques make for an efficient design process. Optional advanced analysis capabilities help designers maximize circuit performance. EMA Design Automation
The Inefficiency of C++,
A widespread "truth" among developers of embedded software is that using C++ results in inferior code size and speed compared with using C. This article will attempt to sort out the facts from the fiction in this statement. By better understanding the underlying mechanisms of the language, a designer can avoid code bloat. In this paper, we will discuss various C++ language features, compare them with C, describe their implications for the ARM code generation, and look at the efficiency of the different ARM architectures IAR Systems
The Move to Standardized
In the world of IT, managing desktop churn is a fact of life. After last decade’s flurry of corporate reorgs, you’re supporting more applications than ever before—sometimes 20+ per desktop. You’re also managing more vendor contracts as a result. Attachmate Corporation.
Avago RF VMMK Devices
Packaging has always significantly impacted on microwave IC and amplifier performance. In most cases, the inherent parasitic capacitance and inductance of the package lead frame and wire bonds set a limit to circuit performance. Avago Technologies developed a bonded-wafer-to-wafer package technology in 2004 and now offers innovative microwave gallium arsenide (GaAs) VMMK devices based on the proprietary WaferCAP™ chip scale package. Surfacemount (SMT), very low cost VMMK amplifier and FET devices are available today and soon to be released diodes and detectors will be added to the VMMK series. Avago Technologies
Automatic Verification
DesignCon 2005 paper on using formal verification to verify the correctness of false-path and multi-cycle path constraints in SDC files. Averant
Microarchitecture Property
The evolution of functional verification has been exceptional over the last 10 years including the introduction of SystemVerilog, reusable testbench methodologies such as VMM and OVM, and raw simulator and formal tool capacity, performance, and debug capabilities. Avery Design Systems, Inc
Robust System Thermal
Today, process technology has advanced to 32nm, resulting in an increase in the number of transistors per unit area and a reduction in package size. At the same time, system designers are trying their best to reduce the system size by increasing the component density on boards, adding as many features in the design as possible to deliver the industries’ best products in terms of space and size. Increased transistor density inside the chip, higher operating speeds, and increased component density on board in modern electronic systems has led to relatively more heat being generated in these systems. All this has made thermal management an integral and critical part of system management in all application domains, including automotive, industrial control, consumer electronics, battery powered systems, and so on. Many systems are equipped with cooling fans to deal with the heat generated. This has led designers to realize the need to come up with cost-effective, reliable, noise-free, and power efficient temperature-based closed loop fan control systems. Cypress Semiconductor Corp.
Reducing EMI in digital
Over the past couple of decades, more and more applications are going digital. Implementation of digital systems is very simple as it is entirely about logic; however, complexity increases exponentially with signal speed, specifically clock synchronization, setup and hold time, jitter, and so on. These problems affect the functionality of not only the individual subsystem but also cause electromagnetic interference (EMI) when high frequency devices are operating in close proximity. Figure 1 shows a typical example of EMI caused by a DVD player on TV reception. Cypress Semiconductor Corp.
Tunable White Light
Undoubtedly, color plays a significant part in our perception of the world around us. We have often experienced situations where the same object appears differently when illuminated with different light sources, giving the impression that the color of an object is also tied to the light source used. This property of the illuminating light source can be quantized as CRI [Color Rendering Index]. The CRI defines how accurately a sample light source reproduces an illuminated object’s color in comparison to a reference light source of comparable color temperature. Figure 1 shows an example where the same object appears differently when illuminated with light sources of different CRI. Cypress Semiconductor Corp.
Photonics Element Library
The Photonic Element Library is specifically designed to provide the photonic industry with a complete backend solution for designing photonic devices. It employs the unique features of dw-2000™, such as our allangle, GDSII native, hierarchical database, and includes a library of parametric optical elements. These photonic elements enable designers to quickly go from simulation to ready-to-manufacture layouts. Design Workshop, Inc.
Characterization Platform
With development costs for ASICs shooting up, prototyping with FPGAs is attractive alternative. This reduces the chance of ASIC re-spins and saves huge money. This platform was developed for ASIC validation and has two high end Vertex 5 FPGAs and 12 connectors each with 500 pins for board stack -up. Dexcel Electronics Designs Pvt. Ltd.
Using 3D Electromagnetic
Continental – a global manufacturer of premium automotive multimedia systems for the OEM market – has applied state-of-the-art electromagnetic simulation techniques in the design of its latest car radio and multimedia systems (Figure 1), helping it to maintain its reputation for high quality, robust products. CST-Computer Simulation Technology
Optimization of a Reflector
In this paper a modular approach using the so-called System Assembly and Modeling (SAM) of CST STUDIO SUITE® is used to optimize a reflector antenna system in a piecewise manner. The results are compared to a full system simulation. It is shown that a similar accuracy to that of the full system simulation can be attained with the modular approach with a much shorter simulation time and using less computational resources. CST - Computer Simulation Technology
Installed Performance
The presence of multiple communication antennas on a tower means that antennas may have to be installed in sub-optimal positions. Electromagnetic simulation can be used to design the antennas themselves, and also to optimise the positioning of the antennas on the tower. This article will describe how multiple solvers in CST MICROWAVE STUDIO® can be combined to predict where to install an omnidirectional stacked bicone antenna array to minimise loss of omnidirectionality. CST - Computer Simulation Technology
Savant - Efficient prediction
CST - Computer Simulation Technology
Low Frequency Electromagnetic
CST STUDIO SUITE includes various solver modules that are ideally suited to the analysis of static and low frequency devices. CST EM STUDIO®(CST EMS) is dedicated to full 3D EM simulation in a wide application range, including sensors, circuit breakers, magnets and coils. CST - Computer Simulation Technology
SCE-MI Macro-Based Interface
As System-on-Chip (SoC) designs grow more complex they demand a higher-level of abstraction to functionally verify all modes of operation. The main focus of Accelera’s SCE-MI Co-Emulation Modeling Interface is to avoid communication bottlenecks when interfacing software models to current hardware emulation platforms during SoC verification. This allows the system to be modeled realizing its full performance potential. In this white paper, we will be discussing the Macro-based SCE-MI interface which utilizes synthesizable RTL macros which provide connection points between transactors and SCE-MI infrastructure. Aldec, Inc.
Test Equipment Plus Develops
Test Equipment Plus, Inc. provides service and support for the used test and measurement equipment market. They also design, manufacture and sell the Signal Hound® line of portable spectrum analyzers. The first prototypes of the analyzers were in need of a spectral filtering solution to be competitive in the market. This case study describes how Test Equipment Plus utilized the CST MICROWAVE STUDIO® electromagnetic simulation tool to design custom filter solutions through virtual prototyping. CST - Computer Simulation Technology
Low Frequency Electromagnetic
In the world of electromagnetic and electromechanical design, state-of-the-art Finite Element simulation is critical to the virtual testing of new concepts and optimization of existing designs. CST EM STUDIO® is a specialist tool for the static and low frequency simulation, design and analysis of electromagnetic devices. CST - Computer Simulation Technology
CST STUDIO SUITE 2014 Brochure
CST STUDIO SUITE® is a package of tools for designing, simulating and optimizing electromagnetic systems, and is used in leading technology and engineering companies around the world. The three pillars of CST’s products are accuracy, speed and usability. CST - Computer Simulation Technology
HercuLeS high-level synthesis
Ajax Compilers ( is a privately funded startup company incorporated in January 2012 in Athens, Greece. The company focuses on the development of electronic design automation (EDA) tools for ASIC and FPGA SoCs, intellectual property (IP) blocks, compilers and code optimization tools. Products developed by AJAX Compilers include a compiler frontend generator, source-to-source code optimizers and intermediate-level profilers, a high-level synthesis environment and an ASIP (Application-Specific Instruction-set Processor) generation prototype. Ajax Compilers
Astra Microwave Speeds
AMPL chose NI AWR Design Environment because it is a powerful tool for MMIC design and at the same time reduces design cycle time. It has an intuitive user interface and is extremely user friendly when compared to other EDA software tools. Productivity, ease of use, simulation speed, availability of models, and innovative technologies are all key benefits of the software for AMPL. The most positive feature of NI AWR software cited by AMPL was an improved MMIC design flow that delivered a reduction in simulation time yet better accuracy with simulation results. AWR Corporation
Accelerating CRCs on
This application note provides some practical examples of calculating a cyclic redundancy check (CRC) on 16 and 32-bit versions of eSi-RISC, and looks at how the user-defined instruction extensions can provide a saving in power, computation cycles and reclaiming memory space. EnSilica Ltd
Sofics hebistor clamps
While High Voltage interfaces are broadly used in many IC applications like motor control, power management and conversion, LCD panel drivers and automotive systems, many IC designers still lack a low leakage, cost effective and latch-up immune ESD protection clamp. This white paper introduces a newly developed protection device and compares it with the traditional approaches, based on measurements on TSMC 0.35um 15V and TSMC 0.25um 40V technology. Within an area of 35.000um², the novel hebistor device with holding voltage above 40V achieves more than 4kV HBM, 200V MM while the leakage and capacitance stay well below typical requirements (<10nA and <250fF). Hebistor devices form a family of high voltage ESD/EOS/IEC protection clamps which are branded under the Sofics PowerQubic portfolio. Sofics BVBA
Migrating Designs to
When migrating to a new CAD tool one of the primary concerns is to save important data in existing designs and libraries. Sometimes it is desirable to translate existing libraries since time and effort have been invested in creating them and you want to avoid having to repeat that development in a new tool. Most legacy designs are typically maintained in their respective CAD tools and new designs going forward are designed in the new tool set. This is primarily due to complexities and compatibility of the data coming from one tool to another. No translation is completely perfect and some tools are more compatible than others. EMA Design Automation
Migrating Designs to
When migrating to a new CAD tool one of the primary concerns is to save important data in existing designs and libraries. Sometimes it is desirable to translate existing libraries since time and effort have been invested in creating them and you want to avoid having to repeat that development in a new tool. Most legacy designs are typically maintained in their respective CAD tools and new designs going forward are designed in the new tool set. This is primarily due to complexities and compatibility of the data coming from one tool to another. No translation is completely perfect and some tools are more compatible than others. EMA Design Automation
Shortening Verification
This paper details how to create useful timing and flow diagrams so they may be utilized to document a design’s functionality and identify the assertions and cover statements necessary for full functional coverage with the CoverAll™ toolset. Solid Oak Technologies
The Importance of Path
This paper details why the inclusion of path coverage is an integral part of an Assertion Based Verification flow for defining full functional coverage. Solid Oak Technologies
Two Major Shifts Impacting
In this whitepaper John Alpine, Spatial VP of R&D, examines the evolution of software development productivity, the point at which ideal productivity is achieved, and what the two major shifts in software productivity will be. Spatial
Inductance calculations
How to calculate the inductance/length of transmission lines from two-dimensional, finite-element magnetic field solutions. Field Precision LLC
Designing a converging-beam
Case study: design of a converging beam electron gun to produce a thin, high-current-density electron beam confined in a solenoid focusing system. Field Precision LLC
Designing solenoid lenses
This paper reviews features of solenoid lenses to focus high-current electron beams. It also discusses how to characterize spherical aberration with a numerical orbit code and how to employ scaling methods to organize simulations for maximum generality. Field Precision LLC
CoSy 2005 What's New
CoSy is doing better than ever. While the market is gradually picking up again ACE Associated Compiler Experts bv
“iWave announced its
“iWave announced its i.MX53 SOM on the same day Freescale announced the availability of its i.MX53 SoC” Bangalore, 1st March 2011, INDIA - iWave Systems Technologies Pvt. Ltd.,   iWave Systems Technologies, a leading embedded design house Headquartered in Bangalore announces a High end, Low cost, Low power SOM based on Freescale’s i.MX53 (ARM Cortex-A8) Multimedia application processor on the same day Freescale announced its i.MX53 processor development platform availability. This I.MX53 SOM module will support the major operating system including Windows Embedded Compact 7/CE 6.0 R3, Android 2.1, Linux and QNX/VxWorks OS platforms. This module is iWave's latest addition to its growing family of multimedia focused products offering high performance processing with a high degree of functional integration, aimed at the growing Automotive Infotainment, Telemedicine, HMI & Display based cluster markets. A dedicated video processor offloads the main core by performing video 1080p decoding and 720p encoding for multimedia applications like playing movies and monitoring cameras.“To speedup the product development at low cost, we have designed this module in MXM-3 form factor. Complex part of the design is implemented in this module and have brought all the signals to the MXM connector, so that anybody can buy this module and quickly develop their own application specific carrier card," said Abdullah Khan – Director Engineering. Alternatively, iWave can also support in developing custom design around its i.MX53 module The key features of this module are i.MX53 / 1GHz processor includes 3D and 2D graphics, 1080i/p video processing, on board 1GB/2GB DDR2 RAM, 8GB eMMC4.41 Flash, 16MB SPI Flash for Boot, 10/100Mbps Ethernet PHY, Micro SD, UART and USB OTG. The module supports MXM-3 form factor of size 85mm x 85mm and support MXM3 edge connector for IO expansion to support Dual LCD, Dual Camera, USB2.0, SATAII, SD/SDIO, CAN, MLB, ESAI, SSI, SPDIF, Video-In, TVout, SPI, I2C, UART and various IO interfaces. Commenting on this new module launch, Mr. Vivek Tyagi, Country Sales Manager, Freescale Semiconductor India Pvt. Ltd., mentioned, “iWave Systems Technologies is a Proactive Design Partner of Freescale Semiconductor. iWave has been involved in bringing out SOM and Reference Designs on Freescale i.MX Platform. The long standing relationship has been beneficial to many of our product customers as iWave reference designs have shortened their cycle time”. iW-RainboW-G11M SOM image: Features/Specifications: Processor: i.MX53 ARM Cortex A8 CPU RAM: 1GB/2GB DDR2 ROM: 8GB eMMC Flash, 16MB SPI Flash On Board Peripherals: 10/100Mbps Ethernet PHY, RS232 Serial port, I2C header, CAN header, USB OTG connector, Micro SD Connector, JTAG Header, On Board Power Connector 314-pin MXM -3 Edge Connector: UART x 3, I2C x 3, SDIO x 3, SPI x 2, Audio SSI x 3, CAN x 1, MLB x 1, SPDIF x 1, LVDS x 2, SATA x 1, Parallel RGB Out x 1,Video In/CSI x 1, USB HS Host x 1, USB OTG x 1, 17 GPIOs, ESAI x 1, Ethernet RMII PHY Signal Interface x1 Form factor: 85mm X 85mm For details, please visit iWave Systems Technologies Pvt.Ltd
Solidify - Static Functional
The growing complexity of ASICs and programmable parts means functional verification is the nightmare that keeps projects managers up at night. Designers are creating ASICs that can't be completely verified in a reasonable time with the talent and computing resources they have available. As a result of the gap between what can be designed and what can be verified, achieving a functionally stable design is difficult and involves many iterations. This paper presents Solidification, a new low-risk methodology for faster debug of ASICs and programmable parts that significantly reduces verification time and effort while increasing quality and robustness of designs. Averant
Using Formal to Analyze
Reset schemes can be difficult to verify in logic simulation because of the non-determinism caused by unknowns (Xs) in the registers and their inaccurate handling in logic simulation which can mask bugs and potentially lead to failures in silicon. Here, we describe a precise formal approach to X-verification of partial and full reset sequences. Insight, from Avery, addresses two kinds of X issues: Avery Design Systems, Inc
Acreo Uses Visual System
Visual System Simulator (VSS) provides deeper understanding of different system aspects and streamlines optimization of various parameters AWR Corporation
Differentiating Noise
Capacitive sensing is emerging as a popular interfacing alternative to switches and knobs in consumer electronics, front panel display applications, and many industrial and automotive sensors. This article describes different kinds of noise impacting any capacitive sensing technology and the methods that can be implemented to overcome different kinds of noise under varied environmental conditions. Cypress Semiconductor Corp.
Making A Product People
Touchscreen technology has existed for quite a while. Why did it take the iPhone to set the mobile world on fire for touchscreens? The key is in technology inflections. With the market shift from resistive to capacitive touchscreens, the invention of “gesture” motions, and the crystal clear, solid feel of glass screens, touchscreens have once again caught the attention of the worldwide electronics buyer. Cypress Semiconductor Corp.
Re-programmable microcontrollers are transforming the nature of embedded applications. Embedded applications in many industrial, automotive, and medical applications implement sensors that require calibration during manufacture to store offset, compensation slope or other configuration data. These systems often have used potentiometers or Serial EEPROM devices to set up and store this calibration information. Data I/O Corporation
XDRC • Enhanced Design
The motivation behind the XDRC is to supply designers with a physical verification tool that can verify the design rules of the most advanced technologies. The XDRC surpasses dw-2000's DRC with improved performance, increased capacity, an expanded set of unique rules and provides designers with the flexibility to combine them into complex scripts. Design Workshop Technologies’ dw-2000 software has become the ultimate tool for designing Optoelectronic, Analog, Mixed Signal and Photonic devices. Design Workshop, Inc.
dw-2000TM HLVS
dw-2000 HLVS is the gateway to advanced features such as electrical layout extraction and network comparison. As is true with all dw-2000 modules, HLE and LVS are well-integrated with the dw-2000 programming environment (GPE) and easily customized to address a wide variety of problems.With these modules, you can easily implement extraction rules for any technology or application. Design Workshop, Inc.
Radar Transmitter Control
Dexcel had designed a product custom made for its customers to ease the Monitoring process for Radar Control and Monitoring System. This system uses all the data from various modules and control the TURN-ON Sequence of a Radar Transmitter. It also keeps on monitoring and scanning all the critical parameters of a transmitter and display the same with help of graphical user interface application on customer PC. Dexcel Electronics Designs Pvt. Ltd.
ESD Survey for Telecommunications
In a previous failure analysis project of a customer’s telecommunications product, DfR Solutions had identified Electrostatic Discharge (ESD) damage to several different GaAs integrated circuits. In addition, DfR determined that these parts had ESD sensitivity as low as 100V, which placed the components under the most sensitive ESD Component Sensitivity Classification of Class 0 (<250 volts). DfR Solutions
3G Video Applications
Now that 3G networks are available in China, innovative 3G commercial applications have become a major means of increasing profitability. To support diverse applications and devices and interconnect them, a 3G application delivery system is required that also provides a user-friendly experience and an increased level of personalization through an Interactive Voice and Video Response (IVVR) interface. Dialogic
Addressing Video Processing
This white paper discusses how the IP Multimedia Subsystem (IMS) network can be used to convert video content so that it is accessible to any user, and how network-based processing techniques could be applied to a wide variety of applications. Dialogic
Are You Ready for HD Voice?
This white paper provides an introduction to HD Voice and discusses its current adoption rate and future potential. It also describes research trials and implementation issues, and sets HD Voice in its industry context. Dialogic
An Implementation of
A Whitted-style Ray tracing accelerator is implemented. It achieves about 2.6M rays per second over realistic 3D scenes. The Ray Tracing core operates 48 MHz on iNEXT with 2- FPGAs. Dynalith
High Performance Collection
A database is an ideal medium for collecting and analyzing coverage. At Oracle, we marry our Oracle database with coverage collection of our verification, and then use SQL to extract coverage metrics on-demand. This presentation outlines an intuitive scheme for database collection of coverage, and presents data showing the scalability and the high bandwidth this scheme is able to handle. Oracle
A full-wave three dimensional (3D)electromagnetic simulator can be used to simulate and visualize the propagation of electromagnetic fields across PCBs. This article will describe how CST MICROWAVE STUDIO® can be successfully used to characterize the response of high-speed channels, and how typical SI results such as S-parameters, Time Domain Reflectometry (TDR) data and eye diagrams can be numerically calculated to predict the response of a channel. CST - Computer Simulation Technology
Feature range and user experience are sometimes seen as mutually exclusive. The ever-increasing complexity of de-sign tasks means that engineers need a broad range of powerful simulation tools and features at their disposal, but only a few of these will be helpful in any one situation. Knowing which feature to use and when to use it can be a skill in its own right. CST STUDIO SUITE® 2013 streamlines the simulation process without compromising on its power or flexibility. CST - Computer Simulation Technology
EMC Simulation for Electronic
By law, products must comply with international EMC standards which have been developed to regulate electromagnetic emissions and the susceptibility of electrical and electronic systems. Striking a balance between EMC and competing design requirements poses major challenges to engineers. By including EMC compliant design at an early stage, additional costly development iterations can be avoided later on down the line. Simulation allows problems to be identified and corrected early in the design process, before the first prototype is built. CST - Computer Simulation Technology
eASIC reduces multi-level
When designing a chip for a high-speed application, the whole channel, including the package and the printed circuit board affects the performance. Find out how multi-level package design times can be reduced with the help of CST. CST - Computer Simulation Technology
CEDA Currents
IEEE Council on Electronic Design Automation (CEDA)
Download Distributor
The EMA Component Information Portal™ (CIP) offers Cadence® OrCAD® Capture CIS users a comprehensive, "off-the-shelf" CIS management environment that includes a component library with a pre-defined set of fields to help take the guesswork out of defining a database schema. A web-based interface enables non-OrCAD Capture CIS users, like those in documentation and purchasing, to have access to the parts database behind OrCAD Capture CIS without using native software. CIP also provides users with a distributor interface that allows them to download distributor parts data directly into their CIS database. With enterprise integration the CIS database will hold data from external systems like ERP, MRP, PLM, PDM etc. EMA Design Automation
Improved Trak models
This paper describes new methods in the Trak charged-particle optics code to find the self-consistent, beam-generated magnetic fields of high-current beams. The modifications are helpful for general work with relativistic electron beams. They are critical for simulations of high-power microwave devices like the relativistic magnetron and the magnetically-insulated line oscillator. Field Precision LLC
High-flux electron-gun
What factors limit the extracted current from an electron gun? How to use computer codes to design high-current electron guns. Field Precision LLC
The paper describes KaiSemi's unique automated FPGA-to-ASIC conversion process. The process which provides customers with a seamless full turnkey ASIC solution, enabling the customer to buy fully compatible replacement chips. KaiSemi's process uses an in-house tool which performs an automated conversion directly from the original FPGA netlist into a functionally-identical ASIC gate-level netlist. KaiSemi
picoPower Labs: SleepWalking
SleepWalking: evaluating input data without using the CPU, on the 32-bit AVR microcontroller UC3L. Saving Power without sacrificing functionalities and performance. Atmel Corporation
The Perils of Aging Terminal
Data on host systems is often the most sensitive on the network. Terminal emulators on the desktop provide access to these systems, but many organizations are still using older products, deployed using best practices from many years ago. Attachmate Corporation.
Safeguarding Cardholder
In 2004, the major credit card companies—including Visa, MasterCard, and American Express—joined forces to create the Payment Card Industry Data Security Standard (PCI DSS). The PCI DSS applies to all companies that store, process, or transmit cardholder account data. Its purpose: to ensure data privacy for consumers via strict security controls across the industry. Attachmate Corporation.
Creating Solutions with
Because the large majority of corporate data resides on host systems, organizations must make that data available to the desktop in order to retain a competitive advantage. The increased demand for host access coincides with a corresponding business trend of buying and customizing off-the-shelf applications, rather than the time-consuming and risky process of building solutions from scratch. Attachmate Corporation.
EpHEMT vs HBTs for PA
Many different semiconductor technologies are currently being used for power amplifiers (PAs) that include a mix of Silicon and GaAs devices – Silicon Bipolar, Silicon MOSFET, GaAs MESFET, GaAs HBT and GaAs pHEMT. Avago uses enhancement-mode pHEMT (E-pHEMT) process for its PA design while most competitors have developed GaAs HBT technology. This paper shows why E-pHEMT technology can provide superior electrical and reliability performance for power amplifier design in wireless communications. Avago Technologies
Building a 3.3 - 3.8
This article presents the design of a 3.3 - 3.8 GHz LNA suitable for IEEE 802.16a WiMAX customer premise equipment (CPE) and base transceiver stations (BTS), built on inexpensive FR4 copper laminate epoxy glass board material using the Avago Technologies ATF-54143 E-pHEMT (enhancement-mode pseudomorphic high electron mobility transistor). Avago Technologies
A High Isolation Buffer
The design and implementation of a high isolation buffer amplifier is presented. This IC uses a two gain stage topology processed in the Avago Technologies Enhancement Mode pHEMT GaAs technology and is packaged in the 8-lead 2mm x 2mm LPCC. It operates preferably from a 5 Volt supply and consumes approximately 35 mA quiescent current. By varying an external bias resistor, the buffer amplifier can deliver maximum output power up to 20 dBm at 2 GHz. It has better than 40 dB of input-output port isolation and operates from 0.5 GHz to 6 GHz. Avago Technologies
Development EpHEMT
E-pHEMT (enhancement-mode high-electron mobility transistor) is a semiconductor process optimized for wireless applications that operate from a single positive voltage source. Ordinary depletion-mode pHEMTs conduct at zero gate bias, or when the drain current, Id, reaches a saturated level (Idss) at a gatesource voltage (Vgs) of 0 VDC. An E-pHEMT shows no conduction at zero gate bias, so that Id = 0 at Vgs = 0V. Thus, it can operate without the negative voltage (required for switch on) required for depletionmode devices. Avago Technologies
Ka-band 2W/4W MMIC Power
The development of PHEMT, 24 to 31GHz 2W/4W power amplifier MMICs are described. The amplifier was designed with highly integrated distributed line-based low-loss power combining design techniques utilizing a 0.15μm GaAs PHEMT production process. Avago Technologies
STMicroelectronics ST7
Cosmic tools for the ST7 family, evaluation version limited to 4k. Cosmic Software
Aava Mobile was founded in 2009 by a team of engineering wizards with a strong background in mobile phone development who wanted to build an opensource mobile device platform for the OEM/ODM market. Aava Mobile’s open devices harness the creativity of developer communities and provide the flexibility to OEM/ODMs and mobile operators to incorporate their own user interface, content and services to differentiate their devices from competitors. AWR Corporation
Legrand Endorses AXIEM
Impressive Performance - Speed of Simulation and Accuracy of Results - More than 10x Better Than Existing Solution AWR Corporation
Sirona cuts development
Sirona products are to be found in all fields of treatment and activities in a modern dental practice. These include, in addition to treatment equipment and instrumentation, the business division CAD/CAM Systems (production of ceramic inlays, onlays, partial crowns etc) and imaging systems with its products for X-Ray diagnosis. Sirona, as a system manufacturer, has the ability to combine products from the various business divisions – an example being CAD/CAM-Systems with 3D X-ray tube devices. The Imaging Systems products range from intra-oral x-ray devices such as the Heliodent Plus range as shown in Figure 1, panorama x-ray devices (Orthopos range) to 3D devices (Galileos range). CST - Computer Simulation Technology
Microdul gains deeper
Microdul produces proximity sensor chips that can be used with remote sensing plates. Changes in plate capacitance are detected by a digital auto-calibrating algorithm. An approaching human finger typically causes a switching operation. This principle is demonstrated in Figure 2. The capacitive switch can be used for many non-contact applications. The main challenge is to develop a sensor which can reliably distinguish between intentional switching operation and environmental interference. CST - Computer Simulation Technology
Quality healthcare aimed at prevention is a trend that is rapidly gaining momentum. Medical devices that capture vital parameters and possess multiple connectivity features enable a seamless flow of information between caregivers and patients. Patient vitals can be located in a centralized repository, which can be accessed and processed by authorized personnel. Home healthcare is booming because of an increase in the aging population, rising healthcare costs, and demand of quality healthcare from remote locations. Technological innovations in the field of medical electronics and communication can drive the cost of healthcare. Applications for health at home include chronic disease management, post operative care, fitness, general wellness etc. Cypress Semiconductor Corp.
Designing Next-Generation
With the trend of increased adoption of consumer electronics in the automotive industry, the design of the center console is undergoing a major shift. This article covers some of the emerging trends which are finding increasing adoption in the center console. These technologies not only provide a seamless human machine interface for when the passenger uses a cell phone or the car navigation unit, but also enable automobile manufacturers to save money, improve reliability, and create a shift in the aesthetics of the car. Cypress Semiconductor Corp.
Comparison of 2.4-GHz
With the penetration of Wireless technology into the human interface device (HID) market, more and more sophisticated HID products are now coming out in the market with integrated wireless technology (wireless keyboards, wireless mice, etc). Often, developers are limited in their options: follow a popular wireless standard like Bluetooth or develop a proprietary protocol optimized for their application. While wireless standards provide the benefit of interoperability, they also introduce complexity and overhead that an application may not require, resulting in a higher system cost. On the other hand, proprietary protocol gives developers flexibility to customize applications at the expense of requiring developers to take on the development process. Cypress Semiconductor Corp.
Acme Cellular_062509.pdf
As a result of inaccurate forecasting, Acme Cellular’s worldwide market share of cellular phone sales was declining. Our product portfolio included five different models of cellular phones (AC-1 through AC-5). Each model is available in 6 different configurations for various languages and service providers. We also have three suppliers for Flash memory devices: Samsung, Toshiba, and Micron. Inventory control, for both unprogrammed (blank) and pre-programmed Flash memories, is critical, as more than 90 different part numbers must be generated and managed. Compounding these forecasting problems were shipping delays due to last- minute code changes. Data I/O Corporation
In the context of electronic product manufacturing, mission-critical applications are those that are vital to the functioning of an overall system. If the application fails, there are typically undesirable results which might jeopardize human lives or may cause significant damage or loss. Examples of these applications are the brake or air bag system in your car, the chip inside a heart monitoring system, or the chip inside the circuitry that controls the navigation system of an airplane. Even though these are dramatic examples of mission-critical applications, our daily lives are full of similar applications with very low to no tolerance for failure. Data I/O Corporation
Comprehensive true all-angle
Physical design is all about maximizing the manufacturable functionality on a single substrate. Increasingly, this requires the ability to design, validate and integrate unconventional devices in diverse manufacturing mediums. Design Workshop Technologies’ dw-2000™ software is a powerful layout creation platform. It supports layout engineers in designing manhattan and complex, curve linear micro devices. For nearly two decades, dw-2000 has provided layout engineers with a proven product used in the physical design of microelectronic, RF, MEMS and photonic structures. Design Workshop, Inc.
New Manufacturing Techniques
Over the last few years the optical component industry has embarked on a planar waveguide revolution. The basis of planar waveguide technology is to create optical waveguides on substrates utilizing manufacturing processes similar to those used in the semiconductor industry. The benefits of this technology are high yield scalable manufacturing, a platform for further optical integration and improved quality over manual assembly techniques. Planar technology is currently being used to manufacture a variety of components including AWG,VOA, OADM and SOA. Design Workshop, Inc.
Onboard(MIL Grade) Image
DCT Engine with Camera Link Interface (DECLI) is an integrated Camera Link Interface and DCT based image compression solution. It can provide interface to any industry standard mono chrome camera (CLI) and compress data by a fixed compression ratio of 32:1 (lossy) and out put the compressed data in serial, HDLC, parallel and PCM formats. Dexcel Electronics Designs Pvt. Ltd.
Bay Talkitec Combines
Because customization, personalization, and convenience are increasingly important to today's customers, BayTalkitec (BTT) decided to create a "Video Yellow Pages" application, which would respond to an SMS message by pushing a video to the sender's 3G mobile phone over a video call. Dialogic
Beijing MXTelecom Develops
Beijing MXTelecom integrated high-capacity Dialogic® boards and Dialogic® HMP Software into its CTI solutions, including its IP Call Center and TICQ platform. One of the IP Call Center installations that used Dialogic HMP Software not only provided seamless PBX-IP connectivity for customers, but also reduced media processing implementation costs by about 60%. Dialogic
CCMENA Develops Advanced
CCMENA designed an integrated IVR, CRM, and contact center solution that would allow the international mobile satellite service provider Thuraya to manage its customer care operations more efficiently. Dialogic
An Introduction to Multimedia
Combining video with voice and text applications to create multimedia services is an important development in the worldwide communications marketplace. Adding video promises to provide a robust new revenue stream for service providers and greatly enhance business solutions, including the contact center. This paper explores market segment trends, multimedia services, key multimedia standards, and the technical components needed to deliver multimedia services effectively. A section on Dialogic and multimedia discusses some of the Dialogic® products that can help make the move to multimedia faster and more cost effective. Dialogic
An Introduction to Multimedia
Combining video with voice and text applications to create multimedia services is an important development in the worldwide communications marketplace. Adding video promises to provide a robust new revenue stream for service providers and greatly enhance business solutions, including the contact center. This paper explores market segment trends, multimedia services, key multimedia standards, and the technical components needed to deliver multimedia services effectively. A section on Dialogic and multimedia discusses some of the Dialogic® products that can help make the move to multimedia faster and more cost effective. Dialogic
Choosing a Dialogic®
This paper supplies high-level and detail comparisons and a set of scenarios to help you decide whether an appliance gateway, gateway subsystem, or HMP interface boards are the appropriate option for an environment and for a particular set of development resources and deployment needs. Dialogic
Verification of OpenVG
System Design Group in Seoul National University (, led by Prof. Soo-Ik Chae) verified OpenVG 2D Vector Graphics Engine using iNTUITION prototyping board which is suitable development kit for video and graphics system including SDRAM, TFT-LCD, etc. Most computational blocks in graphics engine are implemented by dedicated hardware and off-chip SDR SDRAM memory is used. The system is developed on SoCBase platform provided by Center for SoC Design Technology in Seoul National University ( Dynalith
Stone is a design management tool. Version 0.1 of stone supports conversion of Register specification to Dyumnin Technologies
High-Level SCM Best Practices
Promotes some high-level best practices that reflect the authors' experiences in deploying SCM. Perforce Software Inc.
CST STUDIO SUITE 2013 Brochure
CST - Computer Simulation Technology
Nanophotonics and Integrated
This whitepaper gives a general overview on different concepts of photonic crystal cavities. Important figures such as the transmission, the mode volume and the quality factor are discussed. The presented information will help the reader to decide which type of photonic crystal cavities will be most suited for the application in view. A design example for a WDM channel filter is given in order to illustrate the design process for a photonic crystal cavity. Furthermore two experimental examples from recent research are shown to demonstrate the wide range of applications in which photonic crystal cavities could be used. CST - Computer Simulation Technology
EMIT - Rapid Identification
CST - Computer Simulation Technology
8 ways to improve your
Watch this webcast and see how your company can enhance design collaboration, data management, and process tracking to prevent delays and minimize costs. Dassault Systèmes
ELDIS Pardubice Develops
The designer chose NI AWR Design Environment because the software offers good availability of microwave circuit libraries and strong and efficient optimization. With the VBA macro, the complex feeding network was analyzed more quickly. In addition, the designer noted that NI AWR software has good documentation and a collection of “how-to” videos and application notes. AWR Corporation
NI AWR Design Environment
NI AWR Microwave Office provides an easy to use interface and built-in process definition tools that allowed the Nanjing University of Science and Technology School (NUST) to efficiently construct the models for vertically multilayer interdigital capacitors and multilayer spiral inductors for our LTCC design. AXIEM enabled us to easily tune, sweep, and optimize the value of the capacitors and inductors. AWR Corporation
University of Peradeniya
Wideband couplers have many practical applications at microwave frequencies. If realized in an inhomogeneous medium such as microstrip, these couplers yield poor directivity, which results in severe performance degradation. One of the major reasons for poor directivity is the mismatch in the odd and even mode phase velocities, along the coupled lines. Several methods have been suggested for compensating for the phase velocity mismatch, but these are limited to narrow bandwidths. The undergraduate design project described in this success story investigates the design and simulation of a unique wideband coupler that improves directivity by increasing the number of stages of the coupled line coupler, thus resulting in a multistage coupler, which improves bandwidth performance and, with optimally positioned capacitances, delivers improved directivity and phase compensation. AWR Corporation

S2C: FPGA Base prototyping- Download white paper
TrueCircuits: IoTPLL

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