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37071
Solving Engineering File
Optimize the Engineering Design Workflow and Send your Large Files Faster... OpenText connectivity Solutions Group
38266
Understanding Grounding
Misunderstanding how ground is implemented in circuit simulation is one of the most common misuses of electromagnetic (EM) simulators and their results. This white paper discusses the defi nition of ground in EM simulators and how to correctly choose among various grounding options, a topic of special importance to designers using the results in a circuit simulator. Many modern simulators now support the notion of local grounding, where different ports can use different ground defi nitions. New features in AWR’s AXIEM™ 2009 3D planar EM simulator offer extensive sources/ports and de-embedding options, including internal edge, fi nite difference/gap and extraction ports, and per-port, coupled line and mutual group de-embedding. AWR Corporation
38267
A Plethora of Ports:
Electromagnetic (EM) simulation technology software has come a long way since it first became popular for microwave and RF circuit design back in the 1980s. With the sophistication of today’s EM tools, it is sometimes difficult to remember how limited those early simulators were. The author is old enough to remember when a challenging problem for a 3D planar simulator consisted of a coupled-line filter with 1000 unknowns and 3D finite element simulators were stressed by a simple multi-layer via transition in a package. AWR Corporation
38242
A Basic Mathematical
Electronic Design Automation (EDA) has been one of the great enabling technologies for modern electronics, including the class of analog circuits classified by their operating frequencies: RF/wireless, microwave, millimeter-wave, etc. Initially distinct and discrete software tools were developed for (logical) circuit simulation and (physical) layout, and these were later augmented by physical verification (DRC & LVS), system simulation, and electromagnetic analysis (EM). Later still, all of these tools came together under unifying environments providing a common database and standardized graphical (schematic) entry. AWR Corporation
38246
High-Speed Serial Backplane
The benefit to having high-frequency design tools resident on a Vector Network Analyzer (VNA) does not become obvious until the time comes to compare simulation to measurements. At this point, the advantage of a more streamlined work flow -- without the impediment of transferring data to a simulator running on a separate PC or workstation - becomes clear. To illustrate the benefit of such a novel, integrated solution (AWR’s Microwave Office software “inside” the Anritsu VectorStar VNA), this application note follows the design flow for a high-speed serial backplane. AWR Corporation
38195
Clock and Reset Ubiquity:
Today’s SoC integrates a collection of peripherals, memory, graphics, networking and I/O components that originate from a multitude of sources. It could comprise designs from within the company, from other companies or from third-party IP vendors. These independently developed components come together to enable a rich feature set for the SoC. However, accompanying this abundance of features is a significant amount of complexity that needs to be correctly and efficiently handled to render the integration successful. One such source of complexity is that components operate at clock frequency ranges that may be very different from those of their counterparts. The existence of these multiple clock domains and the need for them to exchange information creates a hotbed for CDC bugs to thrive. As a result, CDC verification becomes critical to ensure that metastability is not introduced in the design. In this article, we provide several situations with varying set of examples that showcase the challenges in CDC verification. Real Intent, Inc.
38240
Design and Synthesis
Next generation high power, high and width electronic devices rely on well-designed RF/microwave components for peak performance. In the specialized world of RF and microwave engineering, the design and development of power amplifi ers (PAs) is a specialty within a specialty that requires many years of focused engineering experience and a suitable collection of test and measurement (T&M) equipment. AWR Corporation
38241
Design Flow for Base
Automated synthesis of microwave devices has been gaining in popularity in CAE applications over the past decade. Antenna Magus now brings this capability to the fi eld of antenna design. Antenna Magus provides a structured catalog of antennas (monitor image below) with concise documentation, robust design algorithms, and export models. AWR Corporation
38245
High-Power Amplifier
SYMMIC from CapeSym is a template-based thermal simulator that has been optimized for monolithic microwave integrated circuit (MMIC) design. This application note demonstrates the integration of Microwave Office and SYMMIC. The integration is script-based and requires minimum manual ntervention as compared to non-integrated thermal solvers. The example used here is an extension of the MMIC high power amplifier (HPA) example that is part of the standard Microwave Office set of examples. AWR Corporation
38249
AWR's Support of Polyharmonic
Linear and nonlinear device models are the building blocks of most RF and microwave designs. S-parameters are often used to represent linear devices. As a “black-box” model, they can easily be obtained using a vector network analyzer and distributed for simulation. S-parameters use superposition to equate the linear relationship between incident and refl ected waves at all of the device’s ports. Nonlinear devices, however, distort waveforms such that their behavior cannot be represented through superposition or S-parameters. AWR Corporation
38269
Design and Optimization
3D electromagnetic (EM) simulators are commonly used to help design board-to-chip transitions. AWR now makes life easier for circuit designers with the introduction of Analyst, a full featured, 3D EM fi nite element method (FEM) simulator. The key advantage of Analyst over other available 3D simulators is its tight integration within the Microwave Offi ce® design environment, AWR’s circuit design and simulation platform. This application note highlights the unique features of Analyst by demonstrating the optimization of the transition from a board-to- -chip signal path. The example shows how the ability to access Analyst from within in the Microwave Offi ce environment saves designers time and provides ready access to powerful layout and simulation tools that are not available in typical circuit design tools. AWR Corporation
38244
Synthesizing & Optimizing
Like all RF and microwave components, a distributed filter design will remain only a simulation exercise if it is not created with its manufacturing process in mind. That is, the tight dimensional tolerances required to meet a set of performance goals must be within the capabilities of the filter’s manufacturing process in order to realize a reliable, repeatable filer AWR Corporation
38237
End-to-end Design and
The X-band frequency range has been designated for critical military and public safety applications such as satellite communications, radar, terrestrial communications and networking, and space communications. It is important to ensure that these signals deliver quality, reliable, and secure communications. This application note describes the design and realization of a complex X-band transmission analyzer for use in real-time material testing. AWR Corporation
38258
Leverage Circuit Envelope
Moving to next-generation cellular systems requires new levels of performance from RF power amplifiers (PAs). While designing PAs has always included the challenge of maximizing efficiency while delivering high linearity, never have the tradeoffs been so difficult as they are for 4G/LTE. For instance, the latest higher-order modulation schemes require exceptional linearity throughout both transmit and receive signal paths, yet wireless carriers demand the highest possible efficiency at the system level. AWR Corporation
38265
Exactly How EM Should
Modern RF/microwave design flows make extensive use of electromagnetic (EM) analysis in many ways, and its co-existence and concurrency with circuit design and analysis can not be underestimated. Prior to the circuit design and especially in larger designs, EM tools are used to create “library” parts such as inductors, transitions, and antennas. While these parts are fairly self-contained, they must ultimately be integrated into the overall design where at the very least they must be connected to the rest of the circuit or in a more complex case be coupled to it. During both early and later stages of design, designers will switch from circuit-based models to EM analysis of critical interconnects to better understand couplings and achieve greater accuracy. EM analysis is used again before the design goes to manufacturing, so that the metal in the design can be analyzed one more time to verify circuit performance alongside design rule check (DRC ), layout versus schematic (LVS), and even design for manufacturability. AWR Corporation
38253
Understanding and Correctly
Understanding and correctly predicting cellular, radar, or satellite RF link performance early in the design cycle has become a key element in product success. The requirements of today’s complex, high performance wireless devices are driving designers to assess critical measurements—noise fi gure (NF), 1dB gain compression (P1dB), third order intermodulation distortion versus output power (IM3dBc), and signal-to-noise ratio (SNR)—long before manufacturing begins. Traditional modeling methods such as rules of thumb and spreadsheet calculations (Friis equations) give limited insight on the full performance of an RF link in next-generation wireless products. AWR Corporation
38248
ACE - Automated Circuit
The Traditional approach to RF/MW circuit design – which is the present day foundation for high-frequency wireless design applications – is being pressured simultaneously by an increase in operating frequencies / bandwidth and a decrease in physical footprint size. The result is that the physical design challenges faced by circuit designers are rapidly increasing, while choices for how these challenges should be best-addressed are not. AWR Corporation
38250
Understanding Available
RF system-in-package (SiP) and multi-chip-module (MCM) designs present engineers with the challenge of integrating complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) for digital circuits and gallium arsenide (GaAs) or silicon germanium (SiGe) devices for RF and microwave circuits with soft-board laminates and low-temperature co-fi red ceramic (LTCC) packages. Software used to design these complex circuits must seamlessly bring together synthesis, simulation, and verifi cation solutions via a single interface in order to ensure optimum component design and placement in each technology. It must also construct schematics and perform physical design entry for any technology in the SiP using uniform commands and menu options. AWR Corporation
38268
The Advantages of Multi-rate
Harmonic balance (HB) analysis is a method used to calculate the nonlinear, steady-state frequency response of electrical circuits. It is extremely well-suited for designs in which transient simulation methods prove acceptable, such as dispersive transmission lines in which circuit time constants are large compared to the period of the simulation frequency, as well as for circuits that have a large number of reactive components. In particular, harmonic balance analysis works extremely well for microwave circuits that are excited with sinusoidal signals, such as mixers and power amplifiers. AWR Corporation
38264
Design of a Near Field
Near field communication (NFC) is being developed as a form of contactless communication between wireless devices like smartphones and tablets. This technology enables users to do things like swipe their devices at the checkout stand or wave them over another NFC-compatible device to share information instantly without complicated setups or physical connections. AWR Corporation
38243
Steady State and Transient
Thermal effects in electronic devices are studied to investigate their influence on reliability and electrical performance. Due to the decreasing size of semiconductor devices operating at unchanged power levels, thermal analyses provide circuit designers with important information about device degradation and electro-thermal coupling. Steady state thermal analyses have been performed for many years in electronics reliability engineering to evaluate device lifetimes. Device channel temperature is the most critical parameter to determine in such a reliability study as it is the primary source for thermal degradation mechanisms. Many techniques exist for modeling and measuring device channel temperatures, however large discrepancies are reported in the literature [1]. AWR Corporation
38256
Visual System Simulator
Achieving the highest possible performance from circuits used in third-and fourth-generation wireless systems is driving a tighter integration of previously disparate tools. Certainly, a level of software synergy is essential when designing circuits for use in today’s wireless systems that employ higher-order modulation techniques together with advanced technologies, such as Orthogonal Frequency Division Multiplexing (OFDM), multiple-input multiple-output (MIMO) and digital predistortion (DPD) circuits, to name a few. As this white paper illustrates, AWR’s Visual System Simulator (VSS) and National Instruments’ LabVieW graphical programming nvironment are now co-simulating so as to better enable designers to analyze, optimize, and verify complex RF circuits, subsystems and digital signal processing within a unified framework. AWR Corporation
38261
Upfront RF Planning Speeds
High-frequency technology didn’t earn its reputation as black magic for no reason. Unlike low-frequency circuits, microwave circuits don’t behave in a totally predictable way, so “tweaking” has been an accepted mainstay of the microwave design approach/fl ow. Fortunately, high-frequency design tools have dramatically improved so that tweaking of prototype circuits is much less common, and today’s engineer has powerful tools that can make sense of the black magic. AWR Corporation
38257
How to Optimize an LTE
Long Term Evolution (LTE) is rapidly being deployed by major US carriers and will serve most, if not all, top-tier markets some time during 2012. LTE is often called a fourth-generation (4G) standard, and provides signifi cantly increased peak data rates, with the potential for 100 Mbps downstream and 30 Mbps upstream, reduced latency, scalable bandwidth capacity, and backwards compatibility with existing Global System for Mobile Communications (GSM) and Universal Mobile Telecommunications System (UMTS) technology. AWR Corporation
38239
Improved Circuit Design
To fi ne-tune an RF/microwave design to meet new design criteria, engineers turn to the built-in optimizers within their electronic design automation (EDA) software. A typical optimization case for a microwave filter, for instance, might include goals for in-band insertion loss and return loss, cutoff frequency, and out-of-band rejection. The large number of criteria that the optimization engine then has to take into consideration to create a landscape of “solutions” are more or less random, and, more often than not, quite large. AWR Corporation
38247
Using LabVIEW in the
Many veteran designers no doubt remember how comparatively simple it was to design base station or mobile phone amplifi ers when the only modulation technique was analog and amplifi er performance could be verifi ed using Additive White Gaussian Noise (AWGN). Nowadays, second (and subsequent) generations of wireless networks usher in digital modulation techniques that necessitate the need to stimulate amplifi ers and other circuits with waveforms they actually process in service. It therefore necessitates far tighter integration between the baseband signal processing and high-frequency circuit design tools as well as actual test equipment for both generating these modulated waveforms and evaluating their effects on the performance of the design. AWR Corporation
38262
Hardware in the Loop:
When simulating a complete subsystem such as a wireless communication device or radar receiver, the quality of measurement data becomes essential to ensure that the fi nished product meets or exceeds the demands the system will encounter in service. The measurement data can be used to make changes to the system early in the design process, when those changes can be realized in the least amount of time and at the lowest cost. However, this can be accomplished only if there is a direct link between the system being simulated and the measurement equipment itself—that is, when there is “hardware in the loop.”AWR’s Visual System Simulator™ (VSS) combined with its TestWave™ software provides an end-to-end communications system simulation environment that makes this possible. AWR Corporation
38252
Matching Network for
One of the most common tasks required of an RF engineer is basic impedance matching. AWR’s Microwave Office® software has included this ability for a long time now via a manual ‘step through’ matching process, however, the latest release of AWR’s Microwave Office now supports the addition of an automated impedance matching wizard, coined iMatch, that allows the user to quickly compare different matching topologies and choose the best solution based upon requirements. AWR Corporation
38254
Using Visual System Simulator
The concept of software defined radio (SDR) has existed for many years. Consequently, you can find many descriptions of an SDR. A concise definition of an SDR is a radio in which some or all of the physical layer functions are software-defined. The physical layer function is the layer within the wireless protocol in which processing of RF, IF, or baseband signals (including channel coding) occurs. Many of today’s SDRs have part of the signal processing implemented in software. AWR Corporation
38263
End-To-End System Design:
Architectural tools used by designers of RF and microwave communications systems include budget simulators, spur searching utilities, and frequency planning tools, all of which are often based on spreadsheets or hard-coded algorithms with a non-commercial user interface. Having served designers well, these “home brew” approaches are limited in functionality and/or breadth, unsupported, and are as varied as the designers who create them. While the level of effort to create these tools was great and once acceptable (if only because there was no suitable alternative), few designers today have the time required to build their own design utilities nor massage existing legacy ones to meet growing requirements of today’s communciation systems. This white paper outlines the benefi ts of using a commercial, specialized software program, such as AWR’s Visual System Simulator™ (VSS) software for end-to-end system design, while also embracing legacy approaches with the incorporation of spreadsheet views. AWR Corporation
38259
Integration of Signal
The system supports easy design in cooperation with test and simulation processes using a signal analyzer/vector signal generator, as well as effective optimization of RF components and overall system performance. Using simulation based on actual measurement data reduces the amount of design and prototyping work, cutting R&D time and costs. Moreover, it can help match performance to requirements, preventing over-specification waste and cutting product costs. AWR Corporation
38194
Challenges in Verification
Emerging systems have three dimensions of complexity when it comes to making them CDC-safe. First, the number of asynchronous clock domains in designs can range from the tens to the hundreds for complex systems with many components. Second, the master clock frequencies vary per component. It is not uncommon for the ratio between the fastest and the slowest clocks to be greater than 10. Third, the clock frequencies themselves can change dynamically during the course of chip operation to save power. As a result, CDC verification becomes critical to ensure that metastability is not introduced in the design.

This article provides several situations with varying set of examples that showcase the challenges in CDC verification.
Real Intent, Inc.
2084
WaferMap
WAFERMAP is a scientific software to collect, edit, analyze and visualize measured physical parameters on semiconductor wafers. BOIN Scientific Software
2078
TCAD Tools
TCAD Tools N/A
41284
Reduce Verification Complexity
Verification requirements are growing in all market segments. Ensuring these requirements are met requires design verification that goes beyond traditional design rule checking (DRC), layout vs. schematic (LVS) comparison, and electrical rule checking (ERC). Small and large process nodes alike are affected by these requirements, while both system-on-chip (SoC) and full custom designs also need comprehensive reliability coverage.
Learn how Calibre PERC can help you:
  • Understand the interactions between different power domains
  • Ensure signals and voltage domains are protected for all operating conditions
  • Get easy-to-use, unambiguous debug results without exhaustive test vectors
Mentor Graphics
2036
Micro-Cap V
The Micro-Cap V demo is a limited but working version of the main program, an easy to use mixed-mode analog/digital simulator with an integrated schematic editor. Spectrum Software
2083
Voyeur
Voyeur is a visualization tool that displays a circuit schematic on the screen. N/A
2075
Bsim3
BSIM3v3 code and documentation University of California, Berkeley
12200
60nm and 90nm Interconnect
Section 1
-DSM Effects on RF Modeling
- Simple versus Complex Modeling Issues
- Dummy Metal and Slotting Effects -Spiral Inductor Example


Section 2
- DSM Modeling on Interconnects
- Dummy Metal Effects on Delay and Cross-talk for Long Interconnects

Section 3
- Power Delivery Inductance effects on Large Digital IC performance
-Solving RCLK models for VDD and VSS network combined
-Determining the size and placement of on-chip decoupling capacitances
OEA International, Inc.
2068
Power Optimization and
Power Optimization and Synthesis Environment N/A
2077
Sunsite's /pub/Linux/apps/circuits
Sunsite's /pub/Linux/apps/circuits directory Sunsite
2050
Ballistic
A simple yet powerful layout language, BALLISTIC, has been created: high-level layout code can be written for designing automated opamp generators, standard cell layout generators, and other analog integrated circuits. gdt@eecg.toronto.edu
35549
Multicycle path analysis
By default, a STA tool performs timing calculations based on single clock cycle behavior. There are cases, due to existence of slow logic between flops inside the ASIC/FPGA, where multi clock cycle behavior is required. The best way to explain multicycle behavior is by comparing it against single clock cycle behavior. ASICServe
2065
Nemesis
Nemesis generates tests for stuck-at and bridgeIDDQ faults in combinational circuits, and simulates tests for stuck-at, bridge, and bridgeIDDQ faults in both combinational and sequential circuits. N/A
36762
Verification IP
VIP Synopsys Inc.
15795
Introduction to TimingDesigner
TimingDesigner Movie
(note this movie is 23 minutes long)
EMA Design Automation
45225
AXI HW/SW VERIFICATION
Wave Semi Case Study: With FPGA designs approaching SOC levels of complexity, AXI has become the leading interconnect for IP in large FPGA projects. A significant portion of any AXI design involves software driving the interconnect. This case study covers the basics of AXI and shows how to leverage DPI to verify the same software code in an FPGA as well as in simulation. S2C inc
37671
HES-7 ASIC Prototyping
Co-authored by: Slawek Grabowski and Zibi Zalewski, Aldec, Inc. & Kirk Saban, Xilinx, Inc.

This paper highlights possibilities of ASIC verification using FPGA-based prototyping, considering the latest Virtex®-7 devices and Aldec HES-7 dual Virtex-7 2000T FPGA ASIC prototyping board. In addition, the most common partitioning issues and resolutions are described.
Aldec
2052
Carafe
Carafe is the second generation IFA software designed to explicitly extract the bridge, break, gate oxide short (GOS), and transistor gate bridge/break faults that may be caused by spot defects using the layout of the circuit and given defect parameters. Regents of the University of California
41389
SpyGlass Flow for XILINX FPGA
SpyGlass Lint and CDC are critical analysis tools for RTL designs that identify chip killer problems and shorten design cycle time. This document highlights the issues that come up when taking a XILINX FPGA-based design through the default SpyGlass flow. With a script-ware based approach, the work required to make the design SpyGlass compatible is significantly reduced. The approach takes care of handling Xilinx library files, design files and design constraints. Atrenta
15126
Verilog Test Suites
Verific Design Automation’s Verilog Test Suites cover syntax and semantics of Verilog 2001, Verilog-AMS, and SystemVerilog. Other than conventional LRM tests, Verific’s tests concentrate on the synthesizable subset of Verilog, thus providing superior coverage for EDA products. Verific Design Automation Inc.
42380
Mastering the Magic of
Multi-patterning technology was introduced at the 20 nm node to overcome lithographic limitations in current IC manufacturing processes. While processes like double and triple patterning may sometimes seem like magic, successfully implementing multi-patterning compliance in the IC design and verification flow requires a thorough understanding of multi-patterning techniques and their impact on your design. Learn what multi-patterning is, why you need it, and how Calibre® Multi-Patterning software can help you effectively and efficiently incorporate multi-patterning into your leading-edge designs. Mentor Graphics
36835
X-Propagation Woes: Masking
This paper presents a complete and practical methodology to comprehensively solve the X problem in RTL design. It begins by reviewing common sources of Xs, and describes how they cause functional bugs as well as unwarranted debug that prolong verification cycles. Solving the X problem helps minimize simulation and synthesis iterations and enables various design analyses (e.g. power analysis), normally performed on netlists, to begin sooner. The pros and cons of various point solutions to this problem are described. The technologies discussed include structural analysis, formal analysis, coding for X-accuracy, and simulation techniques such as random seeding of state initial values. It is essential that a complete solution address both X-optimism and X-pessimism woes as well as be applicable to all sources of Xs, facilitate debug, provide coverage analysis, and enable automation, high performance, and usability. The requirements of a complete and practical solution, based on feedback from users who deal with X issues are provided. The summary of our interaction with users is that the X problem is multi-dimensional and needs a holistic solution that brings to bear the combination of structural analysis, simulation and formal analysis to solve effectively. We describe our user experiences and a case study based on our proposed solution. Real Intent, Inc.
34497
BAE Systems - Analog
Analog Office software and PDK support BAE System’s revolutionary mixed-signal photonics chip design AWR Corporation
35044
SystemVerilog Made Easy:
Since the adoption of hardware description languages (HDLs) as the methodology of choice for digital design in the early 1990s, an abundance of EDA tools based on the Verilog, VHDL and, later, SystemVerilog languages have been introduced. Providing full support of these languages for simulation and synthesis purposes turned out to be a large differentiator between EDA providers in the early days. But over time, as the industry started to better understand the languages and their implications, the quality of the EDA tools improved to a point where digital design engineers expect full support of the IEEE standards that define these HDLs. Verific Design AUtomation
34613
You Are In a Maze of
Featured Paper by Rich Edelman, Adam Rose, Andreas Meyer, Raghu Ardeishar & Jason Polychronopoulos

This paper will demonstrate building layered stimulus using OVM sequences and sequencers. Virtual sequences and virtual sequencers will be demonstrated by building a small collection of examples that can be used in layered stimulus verification environments. The main contribution of this paper is a new layering component that performs the standard layering task while minimizing user programming without requiring exotic connectivity, extended components or the use of the factory.
DVCon 2010
41283
Improving Design Reliability
With the advent of more complex design requirements and greater variability in operating environments, electrical overstress (EOS) is one of the leading causes of IC failures across all semiconductor manufacturers, and is responsible for the vast majority of device failures and product returns. Learn how Calibre PERC can help you:
  • Understand voltages at the pin level without SPICE simulation
  • Avoid EOS and identify oxide-breakdown conditions
  • Improve reliability and reduce verification time
Mentor Graphics
41360
How to Achieve Power
Power dissipation is a major concern in modern day IC design. For wireless electronic appliances, battery life is one of the major influencers of the purchase decision and can be an effective differentiator. Mobile phones, PDAs, digital cameras and personal MP3 players are increasingly being sold on the long battery lives Atrenta, Inc.
36247
QuickField 5.9
new release TeraAnalysis
41361
Congestion Mitigation
Early physical design closure is critical for successful SoC delivery. Routing congestion is one of the key aspects of physical design closure. In this paper we have focused on the logical congestion aspects. We have established the need for a solution geared towards RTL authoring and creation teams. Some products are beginning to emerge in the EDA marketplace to tackle the congestion problem described above. SpyGlass® Physical, a new product in the Atrenta SpyGlass family, is aimed specifically toward RTL designers and offers many capabilities to resolve logical congestion issues up front, during RTL development. The product has very easy to use physical rules with debug capabilities to pin point the root cause, as well as simple reports with the congestion status of RTL blocks. Atrenta, Inc.
41368
Atrenta SoC Realization
This White Paper deals with the way SoCs are designed, a process of substantial complexity. This design process is undergoing significant transformation, and those changes are a central part of this piece. Atrenta, Inc.
42379
Pattern Matching: Blueprints
Design patterns have a wide variety of applications in the design, verification and test flows of IC development. From significantly reducing rule deck complexity to simplifying the task of avoiding known yield detractors to enhancing workflows such as design rule waiver recognition, pattern matching has become a useful tool throughout design, verification, and test process. Learn how Calibre® Pattern Matching software can help you implement automated pattern capture and pattern matching in your various IC flows for maximum success at emerging process nodes. Mentor Graphics
33425
ESL anyone
This presentation and talk will present the two major approaches to ESL design entry and what is expected of the designer in each case. A specific coding example will be presented illustrating what is expecting too much of a C to RTL compiler, (and thus gets both the designer and the tool into trouble), plus the coding required to remedy the problem. Open-Silicon
41362
An Automated Approach
This white paper describes a novel approach for memory built-in self test (MBIST) and repair insertion at the register transfer level (RTL). The approach is independent of BIST IP technology and works with any supplier\'s qualified ASIC design kit and BIST libraries. The methodology describes both a bottom up and a top down approach to SoC design and validation - all at the RTL stage. Application of this approach on real industrial designs indicates enhancement of design productivity and shorter cycle time for functional validation. Atrenta, Inc.
41350
Avoiding Pitfalls While
In this white paper we will discuss various types of exceptions and describe how to avoid pitfalls using a systematic verification approach. Implementation tools such as synthesis and place and route make use of this information to better optimize the implementation and achieve better area, timing, power or routability. While timing exceptions are potent tool in the hands of implementation engineers, any mistake in specifying them can result in a chip failure.” Atrenta, Inc.
41365
Combining Structural
Multiple, independent clocks have become a fact of life on SoCs and other complex ASICs. In extreme cases, such as in large communications processors, clock domains may number in the thousands. Clock domain crossings pose a growing challenge to chip designers Atrenta, Inc.
30056
ENABLING ASSERTION BASED
Assertion Based Verification (ABV) has proven to cut debug time in half and has been promoted as the technology having the most impact on reducing verification time and cost. SystemVerilog with ABV has been viewed as the evolving standard for the most complex chip designs.

In spite of the promise of ABV, wide scale use has not materialized. Assertion Based Verification is a difficult technology to implement and is perceived as marginally cost effective. If it were easy everyone would have jumped on it by now.
Zocalo Tech
30672
Cadence PSpice Magnetic
PSpice®, an OrCAD® family product from Cadence®, provides industry-standard solutions ideal for engineers who require accurate analog and mixed-signal simulations. PSpice A/D is a full-featured, native mixed-signal simulator. The robust PSpice Advanced Analysis (AA) tools are used in conjunction with PSpice A/D to improve designs. EMA Design Automation
34010
Semiconductor Weekly
Research Wells Fargo Reseach
41285
Improve Reliability with
Power challenges in today's IC designs create a significant increase in verification complexity. Critical design rule checking of variable spacing rules for densely packed multi-voltage nets is often verified with the traditional use of marker layers, a tedious and error-prone technique. Without an efficient means of verifying variable spacing within nets, designers often play it safe and simply apply maximum spacing throughout specific areas of a design, wasting valuable design area. Learn how to:
  • Optimize design size with correct voltage spacing rules
  • Avoid TDDB within your designs
  • Improve reliability and free yourself from manual marker layers
Mentor Graphics
41364
Constraints Management:
Constraints management is a major concern for designers today and increasing design complexity, coupled with mounting time to market pressure, makes faster timing closure and reduced iterations a necessity. Any late stage constraint change brings with it enormous costs, both in terms of time and money, and can lead to a failed design project Atrenta, Inc.
42293
Analyzing Power Integrity
When a printed circuit board (PCB) includes a power plane that is near to signal traces or other power planes, there is a significant risk of energy transfer between parts of the system. Not only does this coupling lead to power switching noise being transferred into data signals, it also means that power supply systems may demonstrate additional resonances that are not seen in the individual components. This can affect the power integrity of the PCB and may reduce its speed or reliability. This paper will explore some of the potential power integrity issues that can affect a PCB and explain how simulation can be used to help reduce these effects. CST-Computer Simulation Technology
33942
Semiconductor Weekly
Research Wells Fargo Reseach
34635
Common Pitfalls in MIPI
Featured Paper by

Jaspreet Singh Gambhir and Jitendra Puri

MIPI Alliance 2011
36525
Altera video
video Altera Corp.
34549
A Smart Synchronizer
Featured Paper by Priyank Parakh & Steven J Kommrusch

In order to achieve satisfactory verification coverage in an asynchronous design, it is highly desirable to model a synchronizer with all the checks that can help catch the problem. Modeling uncertainty caused by metastable values at the output of the synchronizer is one of them.
DVCon 2011
33858
Well Fargo Research:
Research Wells Fargo
34596
Using SystemVerilog Packages
Featured Paper by Kaiming Ho

This paper details some of the key features and frustrations of using the package construct in SystemVerilog. The package construct is compared to similar features in other languages such as the identically named construct in VHDL and namespaces in C++. Valuable lessons learned over the course of multiple projects in the development of verification environments are described, and the paper makes recommendations for basic DOs and DONTs for SystemVerilog package use. The theme of code reusability is always important, and tips on how packages can be used to achieve this are discussed.
DVCon 2010
35121
Modeling and Verifying
This paper describes a novel method for modeling and verifying cache-coherent protocols using Jasper ActiveModel™ technology. The methodology and benefits of using ActiveModel technology to model and verify the ARM AMBA® AXI Coherency Extensions (ACE™) protocol are outlined. In addition, it describes how an ActiveModel protocol model becomes a valuable piece of system-level verification intellectual property (VIP) used to verify RTL designs. Finally, the collaboration between ARM and Jasper that resulted in the development of the interface-level VIP needed to verify RTL designs supporting the ACE protocol are detailed. Jasper Design Automation
34568
Automated approach to
Featured Paper by Ballori Banerjee , Subashini Rajan & Silpa Naidu

Today's designs contain several hundreds to thousands of registers and memory elements. Starting from documentation to design implementation to verification of each single register, each bit and its property involves a lot of time and complexity.
DVCon 2011
32645
Digital Place and Route
Mixing digital automation with analog customization to provide a state-of-the-art mixed-signal design flow

There is a category of high-end integrated circuits (ICs) – often referred to as "analog-on-top" since the top level description is a SPICE netlist – that predominantly comprise analog circuitry augmented with blocks of digital functionality. Until recently, these digital blocks were relatively small, each typically containing only a few tens, hundreds, or (sometimes) thousands of logic cells. Such blocks were often handcrafted by the analog designers using traditional custom design capture and layout technologies.
SpringSoft, Inc.
35124
Great Connections for
I am struck at how easy it is to get used to “good enough” ways of working. Often we fail to notice new innovations that can make our tasks easier and boost our productivity and reduce risk to success. When asked about connecting to other design team members locally and worldwide, engineers might think of a VPN link to their office computer or the headquarters email server. However, they would be missing the exciting developments of a whole new way of working that brings collaborative resources to bear on the design process, so that design creation, verification and integration is easier and less costly to do. EDACafe.com
41369
Automated Assembly and
Platform-based methodology is projected to become the dominant approach for SoC design in the very near future. Automated assembly techniques equally will become the standard approach for building these designs in order to manage complexity, time to market and development cost. Adopting such techniques can have significant impact on each of these factors and carries a significantly lower startup cost than many people assume. More importantly, these techniques are starting to become a competitive advantage, especially in consumer segments. In this White Paper, we have reviewed the key steps needed to implement automated assembly methods. We have reviewed the costs and benefits associated with these tasks and discussed how they are working today for real designs. Atrenta, Inc.
33047
Gates-on-the-Fly fixes
Logical Equivalence Checking software like Cadence’s Conformal and Synopsys’ Formality create detailed reports of differences and errors, but it is often difficult to find, view, and fix the logic cones involved with the errors. SynaptiCAD’s Gates-on-the-Fly (GOF) can be used to easily find and view these specific logic cones on a schematic so that you can visualize just the paths you need to see without unnecessary clutter. GOF also simplifies mapping from RTL level constructs to their gate-level equivalents, so that you can pinpoint the locations where changes need to be made. And GOF's ECO mode supports both graphical and script-based editing features for tracking ECO changes. Metal-only ECO operations are also supported with an automatic spare gates flow. SynaptiCAD, Inc.
31380
Die Level Process Monitors
In the silicon debug process, the basic question needs to be answered; do I have a process problem or a design problem? Unlike conventional ring oscillator based, scribe line based structures, Ridgetop's patented approach provides fabless semiconductor firms with effective tools to help accelerate silicon debug. Ridgetop's proven die level test structures allow more precise monitoring and troubleshooting for advanced IC design. Self-contained and occupying minimal space, the structures can be used to measure critical mismatch parameters and the extent of NBTI effects (intermittencies). Ridgetop Group, Inc.
33872
UVM Reference Flow Overview
An overview of the UVM Reference Flow community contribution from Cadence. Presentation reviews what is the UVM Reference Flow contents, discusses roadmap and legal considerations, along with other facts needed for users looking to have a standardized reference for the UVM. Cadence Design Systems, Inc.
34504
Clock Concurrent Optimization:
Timing divergence has a critical impact on the economic viability of migrating to sub-65nm process nodes. Clock concurrent optimization (CCOpt) is a revolutionary new approach to timing optimization: it merges physical optimization into clock tree synthesis and simultaneously optimizes clock delay and logic delay using a single unified cost metric. With CCOpt technology, engineers can achieve timing convergence and have a new degree of freedom to design and integrate faster, smaller, lower-power digital chips. Cadence
36463
Randomization and Functional
Modern digital designs reach the scale of complete systems and require support of Constrained Random Test and Functional Coverage in verification. Although VHDL does not have built-in, direct support for those methodologies, there are neat solutions that allow their quick implementation in your testbench. Aldec
32401
PCell Caching in OpenAccess
Cashing in on Legacy PCells

In computer programs, caching is used to store the output from commonly used functions on the disk so that, when executing a repeated instruction, the results may be obtained more quickly without having to reprocess the request. This same mechanism can be used to speed up the display of parameterized cells (PCells) in custom IC design. Some Electronic Design Automation (EDA) tools cache PCells automatically for performance reasons; some require additional licenses; and others offer no caching at all. In addition to the performance benefits, PCell caching can be used to make tool-specific PCells visible in other tools in the design flow.
SpringSoft, Inc.
35299
Expect faster adoption
Integrated Development Environments have been popular in the software world for many years. While the first platforms were dedicated to a single language, modern systems such as Eclipse and Netbeans are structured so that they can be configured for different languages using plugins. This means that the IDE developer can exploit a stable code base and focus on producing a configuration for the language of interest. Since verification testbench writing is essentially a software activity, it was no surprise when IDEs for the popular e language started appearing in 2006. Indeed, there are also IDEs available for the Verilog and VHDL Hardware Description Languages (HDLs) and, more recently, for System Verilog. AMIQ
41388
Analysis of Random Resistive
Traditional netlist-based DFT analysis runs into design rule violations during scan insertion in synthesis and needs RTL designers to modify the design for uncontrollable clocks and resets. Similarly, low fault coverage during ATPG results in designers having to modify RTL to improve observability and controllability causing many design iterations and schedule impact. Atrenta
30194
Reduce Power, Area and
This paper, using an example design, demonstrates how to meet challenging performance, latency and bandwidth goals by using the DesignWare® Interconnect Fabric for the ARM® AMBA® 3 AXI™ while minimizing the total area, power consumption and number of top-level wires. The paper also studies the design requirements and examines the optimization features of the DesignWare Interconnect Fabric used to meet the stringent timing requirements. Detailed technical analysis is provided for the selected architecture, pipelining mode, arbitration scheme and the slave visibility feature employed to reach timing closure for the links with demanding performance requirements. Final results are presented based on the hybrid architecture of the DesignWare Interconnect Fabric used to optimize the infrastructure resulting in a reduction in area, power and routing congestion. Synopsys Inc.
41363
Facilitating At-speed
This white paper demonstrates a solution for facilitating at-speed test at the register-transfer level. The RTL approach is important, because designers and test engineers usually verify the test coverage only at the gate level during the final ATPG stage. This RTL solution thus saves weeks of effort by fixing potential issues up front. Atrenta, Inc.
33528
Sustainable Innovation
At a time when building a new global “sustainable economy” requires that we fundamentally change the way we work and live, High-Tech & Electronics companies are more than ever hard-pressed to create the next generation of innovative and sustainable smart and green products. Dassault Systèmes
33968
Semiconductor Weekly
Report Wells Fargo Reseach
33851
Semiconductor Weekly, Dec. 6
Industry Analysis Wells Fargo Reseach
33990
Get IEEE 1685™ Launches
The IEEE announced today the launch of Get IEEE 1685™, a website where users can download the current version of the standard free of charge. Acellera
35911
DFM Introduction
DFM defines the concept of considering the product from the beginning of the design/planning stage to the finished assembly. Considering all of the aspects that go into the development of a prototype before you begin layout will aid you in developing better forecasts for development and production costs as 80% of all product cost is fixed at the time of design. Omni Graphics Ltd.
34541
TLM-2.0 in SystemVerilog
Featured Paper by Mark Glasser & Janick Bergeron



Transaction-level modeling (TLM) is a methodology for building models at high levels of abstraction, those above RTL. TLM-2.0 is a library that contains classes that implements a methodology for building transaction-level models in systemC and connecting them together.
DVCon 2011
31731
Formal Verification for
Low-power designs have become ubiquitous in today’s world. Designers of consumer and mobile products create aggressive low-power designs to compete on extended battery life. Tethered device designers (e.g., servers and routers) want to reduce cost of ownership. Consumers are also more conscious of “green” design in every area of electronics. Today, low-power designs are so popular that nine of ten new designs implement one or more power management techniques. In fact, every consumer device employs low-power techniques such as clock gating, multiple threshold voltages, and power shut down. Jasper Design Automation
33879
Semiconductor Weekly Dec. 20
Research Wells Fargo Reseach
31440
Cadence EDA360 Vision Paper
Today, systems and semiconductor companies are undergoing a disruptive transformation so profound that even the best-known companies will be impacted. The EDA industry now stands at a crossroads where it also must change in order to continue as a successful, independent business. The disruptive transformation we are speaking of is not about EDA developing new design tools. It is not about new methodologies. It is not about the functional verification crisis, or the move to electronic system level (ESL) design, or any of the issues that have dominated discussions about EDA to date. It is about something much larger. It begins with a shift from design creation to integration in the electronic systems industry, and results in a new focus on profitability. This realization, in turn, opens the way to EDA 360, a new vision for what the EDA industry can become. Cadence Design Systems, Inc.
29306
The economies of outsourcing
In his 2000 book ‘Living on the Fault Line’, high-tech guru Geoffrey Moore (of ‘Crossing the Chasm’ fame) makes an eloquent case for corporations to focus on Core and outsource Context. In Moore’s view, Core are the activities that directly affects the competitive advantage of an organization, in other words differentiate it from the competition. All other activities, and those are often the bulk of an organization, are Context. The important message, of course, is that one should outsource its Context and focus its best and brightest on its Core. The good news is that one company’s Context is another company’s Core. An example is the paper multiplication industry. Having a photocopy machine at work is handy, but once a manual needs to be reproduced for customer ship wouldn’t you rather go to Kinko’s. They pick up and deliver your materials, keep their machines humming 24 hrs a day, and are a lot cheaper than you burning the midnight oil changing your office copier’s toner. The time saved should be used on planning your next product. Verific Design Automation Inc.
34537
Application of SystemC/SystemC-AMS
Featured Paper by Tao Huang & Stefan Heinen



In this paper, we describe the application of the Timed Data Flow (TDF) feature of the recently released SystemC-AMS standard in the context of a 3G modem Virtual Prototype.
DVCon 2011
38724
Time-Dependent Analysis
Featured Paper by M.S. Yeoman

Trefoil cable formation is used where three phases are carried by three single core power cables rather than a single multicore cable. The advantage of installing three single core cables in such a configuration is that it minimizes the induction of eddy currents, which reduce the effect of localized heating, while maintaining the current carrying capacity of the circuit. Trefoil cleats, are structures used to hold the three single core power cables in a trefoil form, along the length of the laid cables. Manufacturers of trefoil cleats are required to physically test their cleat designs to failure in an applied test, where a section of three single core power cables are held with the cleats and then short circuited. The resulting high dynamic electromagnetic forces being produced from the short circuiting of the three single phase cables, need to be held & maintained by the trefoil cleat. These, physical test can be costly in terms of both cost & time. In order to reduce the cost of trefoil cleat design & development, a time-dependent COMSOL Multiphysics model, including currents, induced electromagnetic forces, material plasticity & contact analysis has been set up to fully describe and simulate the dynamic load conditions on the cable & cleat design. Comparisons to physical tests & calculations using the test standard & empirical data show excellent comparisons. The model developed can now be used to quickly assess trefoil cleat designs without the huge expense & time.
Comsol
41349
Requirements for Soft
This white paper focuses on how SoC designers and integrators can effectively assess the quality and completeness of soft IP cores. A methodology for accomplishing this goal is presented, and an overview is provided of the Atrenta IP Kit - an application of the SpyGlass® platform that implements a soft IP quality qualification methodology. Atrenta, Inc.
34515
A Practical Look @ SystemVerilog
Featured Paper by Doug Smith & John Aynsley



Functional verification of today’s large and complex designs is a major challenge and bottleneck. As a result, various tools, techniques, and languages have been developed to automate as much as possible to maximize productivity. For example, automatic testbench generation of random stimulus offers a significant aid in finding obscure and hard-to-find bugs.
DVCon 2011
32827
Dynamic Design Analysis
Static analysis tools provide many types of insight into the design and are being widely used to detect and prevent various potential problems with designs. Applied during various phases of the design project, they can detect minor issues to the most serious errors in designs. Tools in this category include Design Rule Checking (DRC), Clock Domain Analysis, Automatic Formal Verification and Formal Verification Tools. AXIOM Design Automation
34511
Easier UVM for Functional
Featured Paper by John Aynsley

This paper describes an approach to using Accellera's UVM, the Universal Verification Methodology, for functional verification by mainstream users. The goal is to identify a minimal set of concepts sufficient for constrained random coverage-driven verification in order to ease the learning experience for engineers coming from a hardware design background who do not have extensive object-oriented programming skills. We describe coding guidelines to address the canonical structure of a UVM component and a UVM transaction, the construction of the UVM component hierarchy, the interface with the design-under-test, the use of UVM sequences, and the use of the factory and configuration mechanisms.
DVCon 2011
30777
Challenges and Requirements
Traditionally, area and timing have been the major issues faced by Integrated Circuit (IC) designers. Now, power has also emerged as a major concern for three reasons. First, low power is favored by numerous end‐applications, such as cellular phones, hand‐held gaming devices, and portable media players. Second, there is an increase in power density due to higher clock speeds and shrinking process geometries control. Last but not least, most system‐on‐chip (SoC) designs are composed of different blocks running multiple applications with varying power requirements.

Power format standards, like Common Power Format (CPF) and the Unified Power Format (UPF), are evolving to establish a power definition that can be used throughout the design, verification, and implementation stages. While development of a consistent power definition seems promising, it has direct implications on the complex verification issues that engineers face in debugging power‐aware designs and the types of solutions needed to address them.
SpringSoft, Inc.
33409
An overview - Aizyc Technology
Aizyc Technology is a semiconductor design services and SoC IP company. Available IP Cores - SDIO 3.0 Host & Device, USB 2.0 IP, Ethernet IP + TOE, MIPI SLIMBUS. Services include Chip Design, Silicon Validation, Physical Design, Firmware & Embedded systems development. Aizyc Technology
34609
IEEE 1800-2009 SystemVerilog:
Featured Paper by Eduard Cerny, Surrendra Dudani & Dmitry Korchemny

The enhancements to the IEEE SystemVerilog language in the 2009 standard and in particular to the SystemVerilog Assertions (SVA) allow us to create much more useful and versatile checker libraries. They benefit primarily from the following features: checker encapsulation, let declarations, clock and disable inference, deferred assertions, elaboration error tasks, and enhanced property operators. In this paper we first identify the weaknesses of the current checker libraries by examining an example from the OVL library. We then provide a classification of checkers, and show how various forms of effective checker libraries can be created using the new constructs.
DVCon 2010
34995
EASICS NV – Company
This brief company presentation gives an overview of Easics activities and projects. Easics NV
43516
Analyzing RF Coexistence
A typical smartphone handset can contain numerous different RF systems, including multi-band cellular antennas, Wi-Fi, Bluetooth, NFC and navigation systems such as GPS and GLONASS. All these systems need to be able to coexist without causing cosite interference. This application note shows how CST STUDIO SUITE® and Delcross EMIT can be used to investigate interference between antennas on a smartphone, and how potential mitigation strategies can be investigated using simulation. CST - Computer Simulation Technology
39906
High Performance Computing
CST - Computer Simulation Technology
33963
FPGA design tutorial
This FPGA design tutorial covers various issues in the fields of FPGA design, simulation and synthesis. It is targeted towards both beginners and experienced FPGA designers. 1-CORE Technologies
34571
Simple & Rapid Design
Featured Paper by Thomas Alsop, Wayne Clift, Luke Hood & Jeff Gray

SystemVerilog Test Bench (SVTB) is a set of language extensions to the IEEE 1800 SV LRM used to reduce the amount of time and effort required to write tests which exercise SystemVerilog (SV) RTL code. Design Verification or more correctly defined “Design Exercise” is a methodology in which pre-defined basic boundary conditions of a design must be tested before submitting code to the project‟s official codebase.
DVCon 2011
34587
Verifying clock-domain
Featured Paper by Jean-François Vizier, Dennis Ramaekers & Zheng Hai Zhou

Usage of a GALS approach for a SoC implies the creation of several asynchronous paths. These paths can be critical for the system as some of them are part of the system bus. They require special attention during verification.
DVCon 2010
38196
Corporate and Product Overview
Real Intent is the leading provider of EDA software to accelerate Early Functional Verification and Advanced Sign-off of digital designs. It provides comprehensive clock-domain crossing verification, advanced RTL analysis and sign-off solutions to eliminate complex failure modes of SoCs. The Meridian and Ascent product families lead the market in performance, capacity, accuracy and completeness. Real Intent, Inc.
41432
Making Floating-Point
Floating-point arithmetic becomes a widely used format in digital system design. For example, DSP applications often demand high precision while operating with large dynamic ranges. The IEEE 754™-2008 floating-point arithmetic standard fulfills this criterion but it might be extremely hard to comprehend and use. This document discusses challenges associated with debugging floating-point arithmetic designs and explains how to tackle them using the tools available with your floating-point aware IDE. Aldec, Inc.
41912
How A Call For SOS Improved
Milandr, a 15-year-old product company based in Moscow that builds high-reliability integrated circuit (IC) products for the aerospace, avionics, automotive, and consumer markets, discusses the use of Cadence Virtuoso and ClioSoft SOS to reduce cycle time and improve designer productivity. Cliosoft, Inc.
30778
Introducing Functional
Functional verification consumes a significant portion of the time and resources devoted to the typical design project. As chips continue to grow in size and complexity, designers must increasingly rely on a dedicated verification team to ensure that systems fully meet their specifications.

Verification engineers have at their disposal a set of dedicated tools and methodologies for verification automation and quality improvement. In spite of this, functional logic errors remain a significant cause of project delays and re‐spins. A key reason is that two important aspects of verification environment quality – the ability to propagate the effect of a bug to an observable point and the ability to observe the faulty effect and thus detect the bug – cannot be analyzed or measured. Existing methods, such as functional coverage and code coverage, largely ignore these two aspects, allowing functional errors to escape the verification process despite excellent coverage scores. Existing tools are simply unable to assess the overall quality of simulation‐based functional verification environments.

The Certitude Functional Qualification System from SpringSoft incorporates unique technology that measures and drives improvement of all aspects of functional verification quality for simulation‐based environments. This paper describes the fundamental aspects of functional verification that remain invisible to existing verification tools. It then introduces the origins and main concepts of a technology that allows this gap to be closed: Mutation‐based testing. It describes how SpringSoft uses this technology to deliver Certitude, the industry’s first functional qualification solution. Finally, it describes how
SpringSoft, Inc.
34741
Safety Weapon Interlock
SWISS is designed for defense to provide necessary interlock signals to the Ship’s weapon control systems for permitting and prohibiting firing of weapons. It ensures safety of ship, onboard men and machine from possible mid air collision of fired ammunition, close to the ship. Dexcel Electronics Designs Pvt. Ltd.
45434
A New Method to Improve
Tomorrow's memory standards hold the promise of higher performance. With the uncertain future of which protocols will emerge as industry standards many system architects conservatively choose from current DDR standards - adopting a "wait and see" approach. However, the needs to improve system performance and reduce power consumption are still paramount with next generation products. With memory subsystems representing significant influences on these two areas, designers must find new methods to improve the performance of memory sub-systems. The Performance-IP method discussed here is implemented using small, distributed, logic elements requires no code changes and does not require the increase of system clock rates. Performance-IP LLC
30669
Cadence Allegro Design
PCB designers who require state-of-the-art functionality, performance and productivity have always relied on Cadence® Allegro® PCB Design products. Whether it’s the unique real-time, embedded, shape-based routing engine that optimizes the router or the constraint-driven, interactive floorplanning methodology for placing components—the Allegro suite of PCB tools provides you with the most comprehensive and cost- effective design solution that is available today. In this webinar, we’ll demonstrate how you can take a project from inception in design capture, the addition of constraints, through placement and routing, all the way to manufacturing output—without leaving your design environment. You can achieve all of this by using Cadence Allegro Design Entry CIS and Cadence Allegro PCB Editor. EMA Design Automation
34595
Coverage Driven Verification
Featured Paper by Michael Baird

A coverage-driven verification plan defines verification goals in terms of functional coverage points. Each area of functionality required to be tested is described in terms of values, events and combinations of these. SystemVerilog provides covergroups as one way of obtaining coverage statistics to drive the testing activities.
DVCon 2010
25464
PureSpec-Ethernet
PureSpec-Ethernet is a complete verification IP solution for verifying compliance and compatibility of Ethernet designs. PureSpec-Ethernet includes simulation models for MAC and PHY component interfaces; and provides extensive traffic generation capabilities to greatly enhance your design verification productivity. Denali
34265
Active-HDL 8.2
Active-HDL is an integrated easy-to-use FPGA Design and Simulation solution, providing a robust design creation tool suite, a high-performance mixed-language simulator and a multi-vendor FPGA flow manager that controls Simulation, Synthesis and Implementation for industry leading FPGA devices, such as Actel™, Altera®, Lattice®, Quicklogic®, Xilinx® and over 87 popular EDA tools, all-in-one common environment. ASICSoft, Inc.
34516
So There’s My Bug!
Featured Paper by Mike Floyd



Modern verification environments like those built with the Universal Verification Methodology (UVM) more closely resemble software applications than hardware applications. The challenge is that the teams building and debugging such environments are more often trained in hardware verification than software verification.
DVCon 2011
34555
Verification Patterns
Featured Paper by Gordon Allan

Multiple parallel CPU or DSP cores are becoming commonplace in today's complex System-on-chip projects. They are often the right solution to provide architecture that can meet demanding performance expectations at an optimal process shrink / power consumption / price point.
DVCon 2011
34561
From the Magician’s
Featured Paper by Amit Sharma, Abhisek Verma, Varun S & Anoop Kumar

In a few weeks, the Accellera VIP TSC will release the "1.0" version of the Universal Verification Methodology (UVM). This was the next step for the committee after it had released the UVM EA release early last year This has been quite significant because, the three major verification vendors have aligned on a single SystemVerilog Base-Class Library and Methodology for the first time.
DVCon 2011
34554
Optimizing Area and Power
Featured Paper by Alan Carlin, Chris Komar & Anuj Singhania

Power consumption is a key differentiator for semiconductor products targeting the embedded market. The combination of system-level requirements and device-level characteristics presents a particular challenge for verifying the implementation of low power design features.
DVCon 2011
30776
Advanced Scgematic-Driven
Circuit designs continue to get larger and more complicated. Custom layout, like most steps in the IC design flow, has become more tedious and time consuming. Designers are always looking for better tools to automate the process and help them become more productive. Schematic‐driven layout (SDL) is a design methodology that assists designers with the physical implementation of circuits, by providing automation and continuity between logic and layout. SDL relies on device generation technology for automation of the creation of physical layout from schematic elements. SpringSoft, Inc.
32288
Applying Formal Methods
Sun designers and architects now view formal as a tool to understand and expose specification holes and errors. Exploring corner case scenarios early leads to cleaner, more robust implementations. And formal verification can help promote design leverage and reuse. Jasper Design Automation
33010
Ensuring the hardware testing results match RTL simulation results is the key to the strict verification guidelines of DO-254. This paper describes how to replay RTL simulation environment in the real hardware with the same flexibility, traceability and coverage ideal for DO-254 certification. Aldec
34563
Functional coverage-driven
Featured Paper by Christoph Kuznik & Wolfgang M¨uller

SystemC is a versatile C++ based design and verification language, offering various mechanisms and constructs required for embedded systems modeling. Using the add-on SystemC Verification Library (SCV) elemental constrained-random stimuli techniques may be used for verification.
DVCon 2011
30482
Ways of Bypassing CPU
Direct Memory Access (DMA) is one of several methods for coordinating the timing of data transfers between an input/output (I/O) device and the core processing unit or memory in a computer. DMA is one of the faster types of synchronization mechanisms, generally providing significant improvement over interrupts, in terms of both latency and throughput. An I/O device often operates at a much slower speed than the core. DMA allows the I/O device to access the memory directly, without using the core. DMA can lead to a signifi-cant improvement in performance because data movement is one of the most common operations performed in processing applications. There are several advantages of using DMA, rather than the one in which core does a memory to transfer operation and vice versa and this paper discuss all these advantages with various applications of DMA Controller. DMA is used in almost every complex system or subsystems , but its observed that teams either build the DMA controller from scratch for each project for specific application or take the existing DMAC available from elsewhere. Here in this article I have tried to discuss the architecture of DMAC that can be used with any kind of Bus, configuration (parallel, serial transfers), can be connected to any kind of ports, most importantly any kind of software assumptions can be implemented in the DMAC very easily. I call it Universal DMA Controller. MindTree Ltd
34512
OVM & UVM Techniques
Featured Paper by Clifford E. Cummings & Tom Fitzpatrick

The Open Verification Methodology (OVM) and the new Universal Verification methodology (UVM) have a number of methods for terminating the run() phase at the completion of a test, usually via a combination of sequence completion, calls to the global stop_request mechanism and/or the recently-added objection mechanism. Many users also use built-in event and barrier constructs on a more application-specific basis to achieve their goals. This plethora of choices has led to some confusion among the user community about how best to manage this important aspect of the testbench.
DVCon 2011
43307
Reducing Verification
Precise verification coverage measurement remains a significant IC development requirement. By combining the exhaustive nature of formal technologies with accurate Observation Coverage techniques, OneSpin has moved the state-of-the-art forward in this critical area. Download this whitepaper to learn more about the Observation Coverage approach and how this has been leveraged in OneSpin's new Quantify coverage technology for precise, rapid formal and simulation coverage assessment. OneSpin Solutions
45015
Is it time to switch
Six years ago, when OASIS was introduced, we published an article highlighting why it was a positive replacement for GDSII [1]. Since then, users have started adopting OASIS in their flows, with benefits and disadvantages. One of OASIS strengths is its flexibility (unlimited coordinate precision, unlimited number of layers, etc...). But this flexibility has a price in terms of memory consumption and computing time. A new standard, OASIS.MASK, is being introduced to address the requirements specific to photomask layout repre- sentation. This subset of OASIS (and as such fully OASIS compliant)introduces constraints that reflect the real-world limitations of mask manufacturing. As a result, OASIS.MASK interpretation and exploitation is more efficient and reliable. [1]P. Morey. Going from gdsii to oasis. EEtimes, December 2008. Xyalis
31328
ZeBu™: A Unified Verification
Moore’s law continues to drive both chip complexity and performance to new highs every year, and continues to stress and periodically “break” existing design flows. Fortunately for EDA users, the same shrinking geometries that make their design problems tougher are also helping to improve the performance for their EDA tools.

But when it comes to functional verification, traditionally the largest bottleneck in the design process, software-based approaches like simulation continue to lose ground. Why isn’t simulation speed keeping pace with device complexity? Because many new devices like 3G cell phones, internet routers, image processors, etc. require massive verification sequences that would take many CPU-years to simulate on even the fastest PC. These sequences are often a result of the need to run long, contiguous, serial protocol streams or complex embedded software in order to fully verify a new SoC or system design.

Increasingly, embedded software is overtaking the hardware content of SoC devices. The net result is a kind of chicken-egg problem: which comes first - the “final” hardware or the “final” software? Embedded software developers need an accurate model of the hardware in order to validate their code, while the hardware designers need fairly complete software to fully validate their ASIC or SoC. Software developers can sometimes get started using a bare-bones, non-cycle accurate high-level C model of the processor or an instruction set simulator (ISS). Similarly, chip designers can simulate their design along with small code snippets or diagnostics to verify basic functionality. But eventually both these groups need to come together on a common model to verify the complete hardware and the embedded software together. Unfortunately, for most teams that first complete model is the actual silicon.
Eve, Inc.
34551
Addressing the verification
Featured Paper by Chris Schalick

The multi-GHz line rates enabled by SERDES introduce new design challenges in FPGAs, notably signal integrity issues which have given rise to a number of design tools and methodologies. But equally as demanding, if not more so, are the functional verification challenges associated with this complex technology.
DVCon 2011
34597
Low Power Verification
Featured Paper by Jianfeng Liu, Mi-Sook Hong, Bong Hyun Lee, JungYun Choi, HyoSig Won, Kyu-Myung Choi, Harsha Vardhan & Aditya Kher

With the widespread adoption of advanced low power design and implementation techniques in SoC designs, the role of low power verification has been more critical than ever. Advanced low power design techniques, such as power gating, state retention, multi-VDD etc, require significant revisions of the verification methodologies, library infrastructure, advanced CAD tool support and serious engineering efforts to tackle the huge complexity in both implementation and verification.
DVCon 2010
35639
SoC Architecture for
The high-definition video trend continues to drive new consumer products. These products are now moving to higher resolution, more sophisticated video compression, such as H.264, and improved image and scaling algorithms up to 120 Hz. This trend is affecting digital TVs, set-top-boxes, game consoles, and even mobile devices. There is clearly a new high quality, high definition (HQHD) segment forming which requires an exponential increase in SoC processing capability to support the more complex algorithms associated with HQHD. Sonics, Inc.
35912
DFM Tips & Tricks II
Even a single sided a board can be viewed from above or below. Clearly marking all layers with right reading text will enable the board manufacturer to verify the proper orientation for your board. The more layers that are employed to make a board, the more important this becomes. Omni Graphics Ltd.
34552
Achieving First-Time
Featured Paper by Kjeld Svendsen, Chuck Seeley & Erich Marschner

Minimizing power consumption has become a critical requirement in today’s designs. Active power management required to minimize power consumption creates additional challenges for functional verification. IEEE Std 1801™-2009 [1] defines the Unified Power Format (UPF), which enables visualization and early verification of the behavior of a design under active power management during RTL simulation.
DVCon 2011
34553
Low Power Static Verification-
Featured Paper by Kaustav Guha , Ankush Bagotra & Neha Bajaj

UPF2.0 [1], with its ability to define power states and corruption semantics on them, has made low power verification flows powerful. This powerful flow provides more flexibility to a verification engineer to define sophisticated assertions, enabling them to isolate more low power issues in the design.
DVCon 2011
34610
Asynchronous Behaviors
Featured Paper by Doug Smith

Most digital designs inherently possess asynchronous behaviors of some kind. While the SystemVerilog assertion (SVA) language offers some asynchronous controls like disable iff, writing concurrent assertions that accurately describe asynchronous behavior is not so straightforward. SVA properties require a clocking event, making them innately synchronous.
DVCon 2010
35292
Lessons in developing
Using external VIP (Verification IP) brings several advantages including availability, independence in both checkers and coverage, robustness from use in several environments. However, the VIP must be developed so that it is easy for the user to incorporate the VIP into their environment. In this paper we look at practical lessons learned in both the development and deployment of VIP for use in complex OVM (Open Verification Methodology) SoC (System-on-Chip) verification environments. Test and Verification Solutions
35415
JTAG/ BOUNDARY SCAN –
Since the existence of integrated circuitries, there has been the necessity to check their functions. In the case of digital circuitries, a test is quite simple: all possible test vectors are applied in succession, and then the circuitries’ reactions at the outputs (actual value) are compared to the expected patterns (nominal value). If there are no differences the circuitry is correct. GÖPEL electronic GmbH
35726
TSMC Corporate Video
TSMC Videos TSMC
35969
Photronics 2011 Analyst
During this presentation, some of our comments may contain projections or other forward-looking statements regarding future events or the future financial performance of the Company and/or the industry. We wish to caution you that such statements are predictions and contain risks and uncertainties and actual events or results may differ materially. Photronics, Inc.
34513
SystemVerilog FrameWorksTM
Featured Paper by Dr. Ambar Sarkar



Scoreboarding is a critical function required of a verification environment. While much progress has been made in standardizing verification environments with the release of Accellera’s Universal Verification Methodology(UVM)[1], no standardized scoreboarding implementation is currently available.
DVCon 2011
34548
Off To The Races With
Featured Paper by Hans van der Schoot, Anoop Saha, Ankit Garg & Krishnamurthy Suresh

A methodology is presented for writing modern SystemVerilog testbenches that can be used not only for software simulation, but especially for hardware-assisted acceleration. The methodology is founded on a transaction-based co-emulation approach and enables truly single source, fully IEEE 1800 SystemVerilog compliant, transaction-level testbenches that work for both simulation and acceleration.
DVCon 2011
34614
Functional Coverage –
Featured Paper by Alan Fitch & Doug Smith

This paper investigates the implementation of functional coverage in languages such as VHDL and SystemC®1, when for some reason the use of SystemVerilog is not possible.
DVCon 2010
45569
Choosing the best pin
S2C white paper for choosing the best pin multiplexing method for your Multiple-FPGA partition S2C inc
31857
The ROI of Hardware Configuration
Software teams have long realized the return on investment (ROI) of software configuration management (SCM) systems, which have been used by software teams for decades to manage development, improve collaboration, and coordinate releases. In fact, SCM systems have become such an integral part of a software development environment that practically no significant software project is even started without a SCM methodology in place. Over the last decade, hardware design teams have encountered the same market forces as software designers: increased competition due to globalization, mandating the use of the best available engineers irrespective of location; an exponential increase in design complexity; and shrinking market windows. The result has been larger teams of engineers spread across multiple sites, managing complex flows, and sharing a large volume of constantly changing data. They need hardware configuration management (HCM) systems. Cliosoft, Inc.
34536
An Innovative Methodology
Featured Paper by Fabian Delguste, Adiel Khan, Abhisek Verma & Graeme Nunn



The traditional verification approach used in the analog world still lacks some key aspects that have been efficiently deployed to digital verification for years.
DVCon 2011
34611
Stimulating Scenarios
Featured Paper by JL Gray & Scott Roland

The Open Verification Methodology (OVM) and Verification Methodology Manual (VMM) libraries used to augment the capabilities of the SystemVerilog language introduce advanced stimulus generation capabilities suitable for designing large testbenches and verification IP in the form of sequences and scenarios. However, many verification teams struggle to fully utilize these techniques, and end up with testbenches that either only support directed tests, or support randomization while being difficult to maintain and enhance. In this paper, advanced stimulus generation concepts, architecture, and motivation will be described. Tips for a successful stimulus generation implementation will be provided, and solutions from the VMM and OVM libraries will be compared and contrasted.
DVCon 2010
34612
Effects of Abstraction
Featured Paper by Josh Rensch & Jesse Prusi

A multi-layer protocol is a lower-layer protocol wrapped in a higherlayer protocol, for example IP over Ethernet. Multi-layer protocols are challenging because of the linkage between the layers required for stimulus generation for a design under test (DUT) that is aware of and processes both layers simultaneously. This paper will discuss the challenges of verifying a design that supports multi-layer protocols and the use of Open Verification Methodology (OVM) transaction objects to overcome them, particularly in the creation of stimuli.
DVCon 2010
35717
Mixed Signal ASIC Design
Triad Semiconductor (TRIAD) delivers mixed signal IC solutions using a radically different approach that allows you to integrate analog and digital circuitry into an application specific integrated circuit (ASIC) at a fraction of the cost and time normally required. Triad Semiconductor
37534
The Concurrent design
Am interesting experiment run in DAC this year to show benefits and drawbacks of different teams working in parallel. Duolog Technologies
37837
JasperGold Apps - Interoperable
This white paper describes JasperGold® Apps, a family of interoperable formal verification solutions. Jasper Design Automation
38727
Utilization of COMSOL
Featured Paper by L. Teich, A. Hütten & C. Schröder

One of the big advantages of COMSOL Multiphysics is the possibility to implement user-defined partial differential equations (PDE) which can be coupled to COMSOL's predefined physics interfaces. However, using the tool’s standard user interface requires manual implementation of the PDEs and a multitude of problem-specific parameters. This process is not just error-prone but also very time consuming. As an alternative to this manual implementation one can use COMSOL’s Java Application Programming Interface (API) which provides an easy and efficient way to create a user-defined simulation package. Here, we demonstrate the usage of COMSOL's Java API by our implementation of a micromagnetic modeling and simulation package.
Comsol
33972
FPGA Architectures Overview
In this short article we discuss modern FPGA architectures (SRAM-based, flash-based, antifuse-based) and their applications. 1-CORE Technologies
34539
Metric Driven Verification
Featured Paper by Neyaz Khan, Yaron Kashai & Hao Fang



Functional verification has long been a major concern in digital design. Over the years, the huge investment in verification spurred the development of tools and methodologies for systematic and costeffective functional verification.
DVCon 2011
34540
UVM TRANSACTION RECORDING
Featured Paper by Rex Chen, Bindesh Patel & Jun Zhao



SystemVerilog provides a compelling advantage in addressing the verification complexity challenge ─ not simply as a new language for describing complex structures, but as a platform for driving a more efficient, realistic test of the design. It is no surprise then that the adoption of the language for verification purposes has been rapid.
DVCon 2011
34542
Advanced Testbench Configuration
Featured Paper by Mark Glasser



Building robust, reusable testbenches means the testbench elements must be configurable. At its essence, configuring a testbench is a matter of populating a database with name/value pairs and providing a means for testbench objects to access that database.
DVCon 2011
34570
Exhaustive Equivalence
Featured Paper by Baosheng Wang, Brian McMinn, Borhan Roohipour, Ashok Venkatachar, Arun Chandra, Richard Bartolotti & Lerzan Celikkanat

There is an ever-increasing demand for higher performance microprocessors within a given power budget. Such a demand forces design choices – that were once seen only in high-speed custom blocks – to spread throughout the microprocessor core.
DVCon 2011
30666
Designing with Cadence
Cadence® OrCAD® Capture offers a comprehensive solution for entering, modifying, and verifying complex system designs quickly and cost-effectively. Whether used to design a new analog circuit, revise a schematic diagram for an existing PCB, or design a digital block diagram with an HDL module, OrCAD Capture allows designers to enter, modify, and verify the PCB design. EMA Design Automation
30667
PCB Design Fundamentals
Designing a printed circuit board (PCB) can be quite a challenge when you don’t understand the capabilities of your design tools. Creating designs with critical requirements and narrow deadlines requires engineers to have comprehensive knowledge of the CAD tool you use daily. Even understanding some of the fundamental operations like importing / exporting mechanical CAD data, creating a PCB library of footprints, physical constraints management etc., can save time and make your job easier and more productive. EMA Design Automation
34529
Parallel Computing for
Featured Paper by Amit Sharma , Shekhar Basavanna & Srinivasan Venkataramanan



In the functional verification of complex chips, there are several phases where the requirements for the memory and runtime are far beyond the simple, single compute-server capabilities. With multi-core processors being ubiquitous nowadays, EDA tools have emerged over the last several years to provide solutions leveraging these multiple cores through parallel computing to push the limits of memory and runtime limitations of erstwhile simple computer infrastructure.
DVCon 2011
34535
GoldMine: Automatic Assertion
Featured Paper by David Sheridan, Lingyi Liu, & Shobha Vasudevan



We present GOLDMINE, a methodology for generating assertions automatically. Our method involves a combination of data mining and static analysis of the Register Transfer Level (RTL) design. The RTL design is first simulated to generate data about the design’s dynamic behavior.
DVCon 2011
34589
SystemVerilog Meets C++:
Featured Paper by John Aynsley

The OVM and VMM methodologies each provide powerful, flexible and intuitive frameworks for the construction of SystemVerilog verification environments. However, many SystemVerilog users also have models written in C, C++, or sometimes SystemC. Furthermore, the emergence of the SystemC TLM-1 and TLM-2.0 transaction-level modeling standards is having an impact on communication styles within SystemVerlog verification environments. This paper offers practical guidance on using the SystemVerilog Direct Programming Interface (DPI) to integrate existing C, C++ and SystemC code into an OVM- or VMM-based SystemVerilog testbench without jeopardizing portability from one simulator to another. This is achieved by presenting a set of simple, robust guidelines for creating portable DPI code.
DVCon 2010
34966
Customer Video: High
Baseball-playing robot system demonstrates perfect and quick pitching and batting technology. dSPACE GmbH
35725
Over the past decade, Phase-Locked Loops (PLLs) have become an integral part of the modern ASIC design. PLLs provide the clocks that sequence the operation of the various blocks on an ASIC chip as well as synthesize their communications. There are various types of PLLs targeting specific applications. Clock generator PLLs are capable of large frequency multiplication. True Circuits, Inc.
37865
JasperGold Property Synthesis
Property Synthesis Throughout the Design Flow for Application in Formal Verification, Simulation and Emulation Jasper Design Automation
32308
Formal Analysis: A Valuable
The verification of today’s bleeding-edge chips requires the best methodology and tools, including the application of high-capacity formal verification technologies throughout the design flow, from architectural exploration to post-silicon debug. We see this last area, post-silicon debug, as an important value delivered by formal technology for design and verification teams who have not employed formal analysis earlier in the process to get the design right the first time. As case studies demonstrate, using formal analysis to find bugs, fix them, and verify the fixes adds tremendous value in the post-silicon lab. Jasper Design Automation
33390
Post-Silicon Validation
Verifying the current generation of complex SoCs requires the best methodology and tools, including the application of high-capacity formal verification technologies throughout the design flow, from architectural exploration to post-silicon debug. We see this last area, post-silicon debug, as an important value delivered by formal technology for design and verification teams who have not employed formal earlier in the process to get the design right the first time. As the case studies presented in this white paper demonstrate, the use of formal to find, fix, and verify the fix adds tremendous value in the post-silicon lab. Jasper Design Automation
34518
Command Line Debug Using
Featured Paper by Mark Peryer



The mainstream use case for the UVM is to create a verification environment that supports the running of multiple test cases which run sequence based stimulus and use automatic checking and coverage mechanisms to achieve closure on a verification plan. However, there is another important use case which is not so well addressed and that is the interactive debug of hardware and test bench bugs.
DVCon 2011
34530
Mixed Signal Assertion-Based
Featured Paper by Prabal Bhattacharya, Don O’Riordan & Walter Hartong



The increase in mixed-signal content - both in size and complexity – of an SoC demands a change in the existing mixed-signal verification techniques. Although some ad-hoc practices exist today for analog or mixed-signal verification, none of these methods scale to the complex circuit conditions that analog and mixed-signal verification tasks encounter.
DVCon 2011
34531
Linking Multiple Verification
Featured Paper by Jing Li, Nantian Qian & Yuan Lu



More features and more bandwidth capability enabled in our new generation switch chips create a daunting task for functional verification. Our verification methodology includes a top level test environment and many block level tests for key blocks. Both rely on random stimulus to achieve significant coverage.
DVCon 2011
34564
Panning for Gold in RTL
Featured Paper by Rich Edelman, Raghu Ardeishar, Akshay Sarup & Suman Kasam

This paper explains multi-level transaction level monitoring, scoreboarding and coverage collection for existing RTL designs. By applying the ideas in this paper, the reader will understand how to achieve higher level verification on reused or lower level design components.
DVCon 2011
34565
Traversing the Interconnect:
Featured Paper by Prashanth Srinivasa & Mathew Roy

There are several challenges in verifying a complex SoC (System on Chip) on time, like frequent specification changes, which include architectural and protocol changes that impact both verification effort and the delivery schedules. As an example, a SoC of ~140 M gates currently we are working on consists of large sub-chip components having hierarchical interconnects, needs to be comprehensively verified.
DVCon 2011
34598
Where OOP Falls Short
Featured Paper by Matan Vax

Functional verification requires, among other things, dedicated programming constructs and mechanisms. Such are accessible to a wide community of verification engineers today more than in the past thanks to the SystemVerilog language. Along with many verification specific constructs it features object-oriented programming (OOP) framework. OOP has been extremely successful in facilitating reuse in many software application domains.
DVCon 2010
35506
Low Power Design –
The NMI recently organised a one day conference taking a software perspective on low power hardware design verification. While hardware designers are becoming increasingly adept at adding clever power saving features into their designs, it is not always clear how software engineers use them. This day was targeted at trying to bridge that gap between hardware and software engineers. Test and Verification Solutions Limited
35839
SoC Bus Architecutre
SoC Bus Architecutre Palmchip Corp.
32289
Formal Verification Deployment
In this case study, a team with little experience in formal verification describe how they used formal techniques to find real bugs, including some that probably would not have been found with simulation. Jasper Design Automation
32309
Survey of Chip Designers
Over 50 engineers and engineering managers were surveyed at DAC 2009 by Jasper Design Automation as part of a market research and analysis program examining how designers use formal verification across the design cycle. Within eight application areas, respondents indicated which formal technology applications are most interesting and valuable, all the way down to each detailed engineering task within the application areas, and their hierarchy of value. The set of applications used in the survey are current uses of JasperGold and ActiveDesign, as developed by Jasper Design Automation and its customers. Jasper Design Automation
34460
Interoperable IP Delivery
This paper describes the theoretical background, current status and future challenges facing interoperable cryptosystem for safe delivery of Intellectual Property (IP) to be used in VHDL and SystemVerilog design and verification. The system must be reliable, and interoperable, i.e. enable safe use of IP source in a variety of tools. IEEE P1735 Working Group currently develops proposed standard describing such a cryptosystem. Aldec
34534
Plugging the Holes: SystemC
Featured Paper by Pankaj Singh & Gaurav Kumar Verma



Technology advances allows for the creation of larger and more designs. This poses new challenges, including efforts to balance verification completeness with minimization of overall verification effort and cycle time.
DVCon 2011
34547
Transaction-Based Acceleration—Strong
Featured Paper by Chandrasekhar Poorna, Varun Gupta & Raj Mathur

Register transfer level (RTL) simulation run times are severely impacted by the verification requirements of today’s complex IC designs. Due to fierce market demands of increased functionality, the need to serve multiple applications with the same core design, and shrinking time-to-market windows, it has become increasingly challenging to complete the verification plan on time.
DVCon 2011
34588
Experiencing Checkers
Featured Paper by Ben Cohen, Srinivasan Venkataramanan & Lisa Piper

The checker construct is a new feature defined in IEEE 1800-2009; it is intended to facilitate the definition and usage of libraries of assertions and to delineate verification code from RTL. In this paper, we describe our experience in using checkers for the evaluation of a cache controller design. The goal was to evaluate how easy it is to define and then utilize the checkers in a variety of configurations. Checkers were defined to include static concurrent assertions, procedural concurrent assertions, immediate and deferred immediate assertions. The checkers were then instantiated statically and procedurally in the design module. We also experimented with where the checkers are defined and how formal arguments were used. Simulation was used to confirm our results, with both pass and fail assertion results expected.
DVCon 2010
34599
Source Control…$100,
Featured Paper by Jeffrey Wren

Release management is critical to the success of every hardware development environment. However, it is typically the most overlooked and underestimated task in most development teams. In this ever increasing complex world of ASIC and FPGA designs, the ability to manage the changes made by both design and verification members in a sufficient way is needed where one can quickly determine faulty RTL, synthesis, schematic, and layout updates. This paper will address the drawbacks of a typical release flow, and will put forth a proven 5 step process a design team can implement which can be then be automated. . It also presents a case study, where a free open source software tool ReleaseWorks® [3] was successfully used to automate this 5 step process.
DVCon 2010
34989
Asynchronous Reset
The term asynchronous reset is a term used with digital design, but, it is often misunderstood. The type of reset is used in the specification of fields or slave interfaces in CSRSpec and the specification of signals in SystemRDL. There are two types of reset: synchronous and asynchronous. Even though the names may imply otherwise, both types have timing constraints with respect to a clock. Semifore, Inc.
35915
Controlling Signal Timing
Standard reference sources (Motorola's MECL System Design Handbook, for example1.7.1) give several formulas that relate to the propagation delay of a signal along a trace on a circuit board. These formulas have been combined and summarized in Figure 1.7a. The first part of the formula provides the basic propagation time under unloaded conditions. In that formula, a = 1 and b = 0 for Stripline configurations and a = .475 and b = .67 for Microstrip. Omni Graphics Ltd.
30691
S2IBIS3 V1.1
The Most Popular Free Spice to IBIS Conversion Tool IO Methodology Inc.
31841
New Approach to Accelerating
Despite many efforts to automate analog design and layout, these tasks remain primarily a full custom process, ; with the result that analog is occupying a larger and larger portion of the total design cycle time. Efforts to automate analog design have not been successful in the marketplace because the tools have not been able to equal the quality levels of full custom design, are complex to set up and use, and are expensive. Tanner EDA’s new tool forgoes full automation in favor of accelerating the layout process by generating key analog design primitives, such as current mirrors and differential pairs. These primitives are often the most time-consuming aspect of layout and indeed the parts that are critical to the functionality of the silicon. The new tool applies matching techniques to address common processing artifacts, produces the optimal solution for parasitics and silicon area, and creates devices optimized for high yield. Tanner EDA
33517
Accelerating Innovation
Smaller devices with more memory and features, environmental constraints, global sourcing, increased speed and decreased cost—these demands pose significant challenges for the electronics manufacturers who, arguably, have the shortest product lifecycle of any industry. Delivering the latest, greatest, smallest and next "must have" tech toy requires design and engineering solutions that will help the industry evaluate and improve product performance on the fly. Dassault Systèmes
33526
Global Unichip Corporation
Maximizing integrated circuit design and production efficiency with ENOVIA V6

Challenge GUC needed to improve time-tomarket, project schedule control, and quality assurance in response to globalization in the competitive integrated circuit design market.
Dassault Systèmes
34528
Assertion Based Self-checking
Featured Paper by Lakshmanan Balasubramanian , Pooja Sundar & Timothy W Fischer



In this paper we propose a methodology to simplify the verification process by creating a library of small, generic Verilog-A (VA) based assertion modules that can be connected together to form more complex checkers for any circuit. This serves as a good infrastructure for designers to easily build their own checkers. A Cadence infrastructure with schematic elements like symbols and forms are built to make the use of the library of assertions for a module level verification more intuitive and user friendly.
DVCon 2011
34562
Pay Me Now or Pay Me Later
Featured Paper by Paul Graykowski & Andrew Piziali

In order to successfully verify a design, the scope and details of the verification problem must be quantified and measured. These are written during verification planning as the feature set of the design. Each feature has associated attributes that may be quantified with selected values and structurally arranged to reflect its nature, thereby defining its associated coverage model.
DVCon 2011
34569
An Automatic Visual System
Featured Paper by George F. Frazier, Neeti Bhatnagar , Woody Larue & Vincent Motel

Performance analysis is an important aspect of TLM 2.0-based system design. While case-specific performance analysis can be hand coded into any model, it is possible to compute useful performance analysis metrics in a generic fashion for TLM 2.0 models.
DVCon 2011
34606
Tweak-Free Reuse Using OVM
Featured Paper by Sharon Rosenberg

Most companies today aim to leverage existing design and verification IP as part of the design and verification flow. Internal IP is developed, tuned and reused over time to become a major company asset and can be a competitive differentiator. A key requirement for developing a central verification IP (VIP) repository is to avoid the need to understand the implementation details or modify existing IP for use in follow-on projects. In working with many large and small corporations, we find that while many companies strive for such cross-company (and cross-project) component reuse, only a few manage to achieve this goal. This document describes the recurring practices that allow companies to excel in productivity and reuse.
DVCon 2010
34733
SAE Circuits Inc. Video
Video Presentation SAE Circuits Inc.
35779
How to generate code
The following video introduces the alternatives to generate code using the ASD:Suite Release 3 v6.4.0. Press the Play button to learn about code generation using the ASD:Suite: Verum Software B.V.
35914
From Analog to DSP
With an increasing number of companies designing DSP into their products, the divisions between different specialities are falling away. Engineers and designers now have to have some knowledge of analog and digital designing, software engineering and mathematics as well. Omni Graphics Ltd.
38936
Matching Circuit Optimization
Impedance matching is an essential part of antenna design. The input impedance of an antenna needs to be reasonably close to the amplifier impedance (e.g. 50 Ohm), otherwise the signal is reflected back to the amplifier and not radiated by the antenna. In many applications matching circuits consisting of discrete inductors and capacitors, or transmission lines are used to improve the impedance matching characteristics of the antenna. This white paper discusses the optimization of matching circuits especially to antenna applications. Although the design of matching circuits sounds simple, there are many practical considerations that need to be addressed. CST - Computer Simulation Technology
45108
University College Dublin
This project challenged students to design and prototype a wideband sequential power amplifier (PA). Sequential PAs offer similar efficiency benefits to Doherty PAs, but without the inherent narrowband restrictions. As part of the design challenge, a high-efficiency, broadband, 45 W peaking PA was required. A broadband Lange coupler for use as the output power combiner was required as well. Both of these designs were to be used in conjunction with a preexisting 10 W main amplifier. AWR Corporation
30031
EasyCODE
This is where EasyCODE customers will always find the latest versions and updates for their products. We invite customers with older versions and interested users to download and test these product versions, free of charge and with no obligation, so they can see for themselves on the basis of their own daily requirements just how beneficial EasyCODE can be. EASYCODE GmbH
30413
Design and Verification
We propose a new methodology flow which will allow the visual definition of a complex SoC through instantiation of parametric IP such as processors, SDRAM controllers, DMA engines, on-chip buses, peripherals, switch matrices and coherency directories, coprocessors, etc. Script based automation helps in integrating any IP with any configurations ,selects relevant and corresponding Verification IPs(in-house developed-if Design IPs are standard), uses suitable Bus Wrappers(OCP,EBI,Avalon,MicroBlaze,PicoBlaze,PIF,AXI,AHB,APB,Generic and others) and stitches all the components design as well verification(synthesizable testbench components ) together and making use of TLMs,BFM (replacing CPUs with Master BFMs) or Process Core based designs creates an CSOC environment. The framework reduces the time to build integration and verify the functionality-it also has the complete set up from assembler to DFT. MindTree Ltd
30557
Enhanced Design Reuse,
Designers reduce board layout and placement time from weeks to minutes through CircuitSpace® AutoClustering™ technology, intelligent design (IP) reuse, and replication. Reductions in PCB design time have a direct impact on time-to-market for new products, which directly correlates to profitability. EMA Design Automation
31858
New Approach to Accelerating
Despite many efforts to automate analog design and layout, these tasks remain primarily a full custom process, ; with the result that analog is occupying a larger and larger portion of the total design cycle time. Efforts to automate analog design have not been successful in the marketplace because the tools have not been able to equal the quality levels of full custom design, are complex to set up and use, and are expensive. Tanner EDA’s new tool forgoes full automation in favor of accelerating the layout process by generating key analog design primitives, such as current mirrors and differential pairs. These primitives are often the most time-consuming aspect of layout and indeed the parts that are critical to the functionality of the silicon. The new tool applies matching techniques to address common processing artifacts, produces the optimal solution for parasitics and silicon area, and creates devices optimized for high yield. This paper outlines explains how. Tanner EDA
34572
Getting Rid of False
Featured Paper by Matthieu Parizy & Hiroaki Iwashita

The recent years have seen LSI design complexity continuing to rise sharply. This phenomenon translates itself in the design specifications as they include non-deterministic parts more and more frequently. For example, in cases of designs using packets for data transmission, packets transfer order is determined by precise rules. But, depending on the timing of the transactions, the final order might be hard to predict.
DVCon 2011
34605
Testbench Configuration Mantra
Featured Paper by Stephen D’Onofrio

All testbenches, even the simplest testbenches, need some kind of configuration knobs (sometimes called configuration fields or configuration parameters) that are used to control setting up some feature in the verification environment. Ideally, the environment also includes some kind of mechanism that allows test writers a way to override a configuration knob’s default value. Configuration knobs are typically setup in the testbench during the building phase and directly used for DUT (Design Under Test) initialization. There are various categories of configuration knobs including (but not limited to) testbench topology knobs, simulation specific knobs, verification component knobs, and testbench specific knobs.
DVCon 2010
34763
Silicon Realization—A
While Silicon Realization encompasses most of what the industry has defined as traditional “EDA,” it goes far beyond this definition by outlining a deterministic path to silicon that is broader, more efficient, and more effective than today’s point-tool based approaches. In its fullness, Silicon Realization addresses the business and technology challenges of complex silicon development, and enables design, implementation, and verification teams to attain higher levels of productivity, predictability, and profitability. Cadence Design Systems, Inc.
25820
Graphical Embedded System
The Flight Computing System of a Novel Nano-Satellite takes advantage of the NI LabVIEWTM Embedded Module & the Low Power Mixed Signal ADI Blackfin® Target ZMobile to Achieve Precise Spacecraft Attitude Determination & Control. The spacecraft “PurdueSat”, classified as a nano-satellite, is currently being developed by the School of Aeronautics and Astronautics at Purdue University. Schmid Engineering AG
30193
DesignWare SATA AHCI
This application note describes how to configure and connect the DesignWare® SATA AHCI IP core to the Synopsys PHY in a multi-port AHB-based configuration, and provides an analysis of the expected throughput on each port based on assumed system parameters. The expectation is that a user should be able to take this example and insert actual system parameters to come up with a performance estimate. We will look briefly at the architecture of the core to enable a better understanding of the subsequent sections describing the configuration and performance calculations of the core. Also, note that while this document only discusses the performance of an AHB-based configuration, the option to select an AXI-based configuration will be available in the near future. Due to the nature of the AXI-bus, which allows for overlapping transfers, we expect an increase in the performance of a multi-port configuration. Synopsys Inc.
31256
Invarian Addresses Sign-Off
IC designers responsible for the physical implementation of the design face a huge problem of design sign-off analysis. Today, they need to use different tools to verify the various design aspects, such as timing, power, voltage drops, and chip temperature. The problem is that each of these analyses needs the results of all the other analyses. Therefore, typically, these tools are run sequentially in a flow, so that the results of one tool can feed the next tool. Invarian
32745
Fundamentals of NAND
This white paper presents very important information for managers, engineers, and system architects who are working with NAND Flash memory. Eureka technology
34465
Facilitating Unreachable
Code coverage is a popular method to find design bugs and verification loopholes. However, once a piece of code is determined to be unreachable, diagnosing the cause of the problem can be challenging: since the code is unreachable, no counterexample can be returned for debugging. Therefore, engineers need to analyze the legality of nonexistent execution paths, which can be difficult. To address such a problem, we analyzed the cause of unreachability in several industrial designs and proposed a diagnosis technique that can explain the cause of unreachability. In addition, our method provides suggestions on how to solve the unreachability problem, which can further facilitate debugging. Our experimental results show that this technique can greatly reduce an engineer’s effort in analyzing unreachable code. Avery Design Systems, Inc
34519
Consistent SystemC and
Featured Paper by Rainer Findenig, Thomas Leitner & Vokan Esen, Wolfgang Ecker



In today’s hardware development, SystemC code is widely used for virtual prototyping, where an abstract system model is used to do an early exploration of the hardware implementation as well as software development. The synthesis tools, on the other hand, conventionally still rely on VHDL as the entry language.
DVCon 2011
34532
Power-aware IP and Mixed-Signal
Featured Paper by Luke Lang



Power intent verification, whose complexity increases exponentially with the number of power domains and the number of different power states those domains can assume, is further complicated by the need to integrate digital and mixed-signal IP blocks. Digital IP blocks may be complex enough to have their own advanced low power techniques implemented internally.
DVCon 2011
34533
Low-Power Verification
Featured Paper by John Decker



Low power has quickly become a primary requirement for a large percentage of designs. As companies rush forward to incorporate the latest low power features, they are faced with the growing challenge of how to verify these complex structures and ensure successful silicon.
DVCon 2011
34543
Comparison of TLM2-Quantum
Featured Paper by Wolfgang Ecker, Volkan Esen, Rainer Findenig, Thomas Leitner & Michael Velten



Virtual Prototypes (VPs) based on Transaction Level Modeling (TLM) have become a de-facto standard in today’s SoC design, enabling early SW development. However, due to the growing complexity of SoC architectures, full system simulations (HW+SW) become a bottleneck especially if a high timing accuracy is required.
DVCon 2011
34557
Stepwise Refinement and
Featured Paper by Ashok B. Mehta, Mark Glasser, Shabtay Matalon & Dan Gardner

For ultra-scale SoC designs that are now commonplace, it has become impractical to use only traditional RTL design and verification techniques. ESL methodologies, used for designing at levels of abstraction above RTL, are instrumental in determining design feasibility, honing requirements, and experimenting with architectures and algorithms to meet functionality as well as performance and power requirements.
DVCon 2011
34593
Combining Simulation
Featured Paper by Aneet Agarwal & Gaurav Gupta

With design complexity growing by the day, the need for verification technologies that can complement simulation based verification is also gaining momentum. Formal verification has clearly emerged as one of the strong candidates. In a typical simulation based verification cycle, the number of bugs reported grows exponentially in the beginning, but this number shrinks rapidly thereafter in the cycle and what remains is a few difficult to find corner case issues.
DVCon 2010
34607
Understanding the Low
Featured Paper by Dr. Gary Delp, Erich Marschner & Kenneth Bakalar

We define four abstract models in common use today for electronic design—electrical, digital gate, digital RTL, and transactional—and discuss the relationships among them. The new low-power model described by IEEE Std 1801-2009 UPF is introduced, and its relationship to the other signal-level models for digital and analog design is defined.
DVCon 2010
34615
Efficient Simulation
Featured Paper by Chao Yan & Kevin Jones

With the increasing complexity of systems, the current simulation based circuit verification used in industry are becoming more expensive while providing low coverage. The paper presents a systematic way to reduce the verification time by optimizing the execution order of test cases. Compared with the default order maintained by engineers, the optimal order can achieve a high coverage in a short time as it guarantees running the important test case first.
DVCon 2010
34708
Timing efficient cell
Pin multiplexing is a common practice applied in order to save large number of pads in an SoC. This reduces the Die area of the chip but impose a number of limitations, like requirement of dedicated, complex pin muxing circuit. Traditionally there are three major types of pin multiplexing circuits which are in use; arbiter based , resgister configurable and priority muxing . Out of these , priority muxing simplifies the muxing strategy as it muxes the various functions together on the basis of timing criticality , also it utilizes the IP’s in built select signal . In this paper we propose a novel MUX cell design which can be applied at the places where priority muxing is used. This muxing strategy enables muxing of functions with equal timing criticality together at one single pad even with the priority intact. Which in turn limits the number of high driving pads in SoCs hence saving power and area both? The proposed circuitry is technology independent and also saves area . This circuit is applied in a SoC at 90nm technology by replacing traditional priority based pin muxing and almost 72% area saving and significant interface frequency increase is achieved Freescale Semiconductor
35067
Analogue Behavioural
The goal of this presentation is to illustrate the requirements for automated analogue behaviour modelling techniques from the viewpoint of the designer. In the first paragraph the reasons for using behavioural models are explained. Next the desired features of such techniques are given in general terms. Finally some of the available methods and tools are presented as an example. EDXACT SA
35324
Processors
Processor verification typically involves simulating the processor core(s) with their associated memories, loading those memories with diagnostics and letting the processors execute the code. A series of external checkers verify that the processor is functioning correctly by comparing it to a C++ instruction set reference model. EVE USA Inc.
35526
Remcom’s XFdtd and
Once modeling the antenna array is completed using XFdtd, the sample far-zone patterns can be sent to Wireless InSite to analyze in-situ performance. Remcom
35573
Antenna Design
IMST offers a wide range of antennas from standard designs to tailored solutions for many different applications. IMST GmbH
35617
Simbeor Touchstone Analyzer
S-parameters quality assurance and macro-modeling automation with Touchstone Analyzer tool in Simbeor 2011 (Macro-Modeling) Simberian Inc.
35727
HIGH SPEED CMOS ANALOG-TO-DIGITAL
The thresholding inverters are the key to the TIQ based ADC circuit. For an n-bit ADC, total (2**n)-1 TIQ comparators are required. Each of the (2**n)-1 TIQ comparators are different from each other. We use special layout technique to generate (2**n)-1 unique comparators, the Systematic Parameter Variation (SPV) technique. The SPV technique is based on the spice parameter provided by the chip fabrication vendor. Micro Magic, Inc.
38417
Whats Behind Digital
Like any new technique that is introduced in the market, digital power control must first prove that it offers important advantages over state-of-the-art analog techniques. In this vein, the first and foremost issue to be addressed is the price, and the secondary considerations are converter size, performance and efficiency. This article covers these issues and also discusses digital power control from a broad standpoint. ZMDI
42309
Understanding and Reducing
Achieving the least possible delay in a video capture, streaming, and display system can be surprisingly affected by the specific H.264 encoder near the beginning of that flow. Read this white paper to learn more about what determines latency, and how to pick the best encoder for achieving low latency in your systems. CAST
30414
Design of Robust System
The Paper describes a model based approach to improve the robustness and re-liability of an embedded system with respect to real-time performance. It charac-terizes how real-time simulation models are generated, run and analyzed to gain knowledge of the dynamic system behavior. The system’s reactions to dynamic stimuli can be predicted without having to implement all hardware and software. A study with an automotive car body control unit illustrates how the timing model is developed parallel to the development progress. Findings and improvements are listed. Besides the technical aspects, the business impact for the current and future systems proves significant advantages of the chosen approach. INCHRON GmbH
32307
Toward Harnessing the
The increasing complexities of modern SoCs and short time-to-market requirements have made efficient reuse of in-house and 3rd party IP mission critical. Since most IP requires some degree of modification before reuse, it’s critical to address the root problems of efficient comprehension, modification, and re-verification in IP reuse.

This paper describes a promising new technology and methodology that consists of putting IP through a "reuse enabling" process. The resulting database is used by the IP consumer with an analysis tool that allows both dynamic association of the relationship
Jasper Design Automation
34273
Cirexx Presentation
Company Presentation Cirexx Corporation
34527
High-Level Synthesis
Featured Paper by Thomas Bollaert



In this paper, we will describe how a complete graphics processing pipeline was implemented using an HLS methodology. As with most real-life applications, this design consists of a complex mix of control logic, datapaths, interfaces, and hierarchy.
DVCon 2011
34538
Plan & Metric Driven
Featured Paper by Gregg Sarkinen



This paper discusses the experience of using plan and metric-driven verification on a recent mixed-signal integrated-circuit (IC) prototype at Medtronic. The design consists of digital and analog circuits which traditionally have been verified with unique tools and methodologies to perform simulation tests.
DVCon 2011
34550
CompMon: Ensuring Rigorous
Featured Paper by Robert Adler, Sava Krstic , Erik Seligman & Jin Yang

Intel defines numerous forms of reusable IP that are leveraged by many projects across different divisions and business groups. In order to ensure the successful reuse in the various system topologies demanded by Intel design teams, compliance of the IP to the specification is critical.
DVCon 2011
34592
Formal Methods to Verify
Featured Paper by Kesava R. Talupuru

With shrinking process geometries, static and dynamic power are increasing rapidly, forcing designers to use a variety of implementation techniques to control power. MIPS Technologies processor cores designed for low power applications use multiple power modes and employ a Power Manager to ensure correct transitions between these modes. This paper focuses on the verification of the Power Manager in the context of the – MIPS 1004K™ Coherent Processing System (CPS), in which various software and hardware events can control switching of power states. Without exhaustive verification of the Power Manager, the power management functionality of the design cannot be guaranteed. This paper discusses on how we successfully used formal methods to verify the Power Manager.
DVCon 2010
34601
Reusing Testbench Components
Featured Paper by Ritero Chi & Xiaolin Chen

Simulation and formal verification traditionally have been treated as completely separate processes. Simulation is procedural and dynamic in nature, highly efficient at testing basic functionalities, but can be difficult to control to target corner case scenarios. Formal is static in nature and highly efficient at finding corner case bugs, but it has serious capacity limitation due to state explosion. Each has its own advantages and limitations.
DVCon 2010
34602
Using Model Checking
Featured Paper by Xiushan Feng, Joseph Gutierrez, Mel Pratt, Mark Eslinger & Noam Farkash

RTL-to-gate logic equivalence checking is a very critical step inside circuit design flows. It is used to make sure the gate-level circuit doesn’t alter functional behaviors of the RTL. Of the various commercial logic equivalence checking tools, Combinational Equivalence Checking (CEC) tools are often used to prove equivalence between RTL and gate due to their high efficiency and good scalability. However, unlike Sequential Equivalence Checking (SEC), which traverses the product Finite State Machine (FSM), combinational equivalence checking proves equivalence for combinational circuits (i.e., Equivalences are formally verified for combinational logic cones between the state points.).
DVCon 2010
35326
Electronic-System Level (ESL)
ESL Virtual Platforms are powerful tools to enable early software development and architectural exploration. However, there is often a need to integrate RTL models into the ESL environment, either for legacy blocks, or because a cycle-accurate model is required. EVE USA Inc.
35502
Benchmarking Functional
This article describes “asureMark™ ” ‐ the Functional verification Capability Maturity Model (FV‐CMM™) benchmarking process developed by TVS to help the user measure the maturity of their verification processes and to provide a framework for planning improvements. Test and Verification Solutions Limited
35579
65nm Migration
33 modules including RF blocks with inductors. IN2FAB Technology
35786
UML and Embedded
UML and Embedded Willert Software Tools GmbH
36123
Considerations for Bulk
A group of leading semiconductor companies have developed a roadmap for leveraging CMOS designs intended for manufacturing on bulk silicon to fabricate ICs on fully depleted silicon-on-insulator (FD-SOI) substrates with ultra-thin buried oxide layers, producing chips with improved performance and lower operating power. This white paper shows that porting circuits from bulk silicon to FD-SOI can be very direct, depending on the FD-SOI technology used by a specific chipmaker. SOI Industry Consortium
37277
Developing robust power
Power line communications (PLC) is a global technology with worldwide interest in its development. In its simplest terms, PLC modulates communication signals over existing power lines. This paper highlights specifications for several PLC alliances and specifications and discusses new proprietary PLC technologies. Texas Instruments
30412
Verifying Hardware and
i have been ardent fan of Toyota manufacturing.Toyota was the first company who streamlined the processes and quality matrix in the factory units , established a flow and performance management in for the workers and implemented a methodology to track the production.This was indeed very different from the Ford(American) and other European companies who till then have been very much stressing on the luxury ,customization etc etc.. MindTree Ltd
30584
Efficient model-based
State of the art

The InfiniScale flow
- Modeling
- Sizing
- Parametrical Yield optimization
InfiniScale®
30665
Cadence OrCAD Layout
Cadence® has begun the End-of-Life process for Cadence OrCAD® Layout technology based products EMA Design Automation
30670
Managing Electrical Constraints
Cadence® Allegro® Design Entry CIS integrates a proven schematic-design-entry system with a robust component information system (CIS). Whether used to design a new analog circuit, revise a schematic diagram for an existing PCB, or design a digital block diagram with an HDL module, Allegro Design Entry CIS allows designers to enter, modify, and verify the PCB design. It also promotes reuse of preferred components and known good-part data. EMA Design Automation
30697
ARM On-Chip Debug Interfaces
When selecting and evaluating debug interfaces and tools for ARM microcontrollers many aspects have to be regarded. This article provides some guidance what should be taken into consideration. More detailed information is available from ARM or the according chip manufacturer. iSYSTEM AG
33996
ENABLING ASSERTION BASED
Assertions are properties or facts describing the required and forbidden behavior of a design. They are “executable specifications” that are monitored during simulation by assertion checkers included in the design file. Zocalo Tech
34556
An experience to finish
Featured Paper by Dae-Han Youn, Sik Kim, Byeong Min & Kyu-Myung Choi

Use of behavioral description and HLS (high level synthesis) flow has allowed designers to shorten design TAT (turn-around- time) with its better performance in hardware description, functional simulation and RTL generation when it compared to the design flow with RTL designs.
DVCon 2011
34586
Strategy and Environment
Featured Paper by Erik A McShane & Srini Iyengar

In this paper, we introduce the concept of full-chip mixed-signal validation (FCMSV) for SOCs, in which any top-level ports of an analog discipline are represented as real-valued signals for validation simulations. Secondly, it exploits SystemVerilog syntax, especially “real” ports, to create one testbench suite that spans a project from top-down development to final bottom-up implementation. Thirdly, it presents a global strategy to improve simulation speed by targeting specific analog blocks for replacement by BMODs. This methodology is a generic strategy independent of EDA tool. The methodology and environment outlined in this paper have been successfully applied to validate three successive projects.
DVCon 2010
34591
COMPREHENSIVE SYSTEMVERILOG-SYSTEMC-VHDL
Featured Paper by Rudra Mukherjee, Gaurav Kumar Verma & Sachin Kakkar

Due to increased complexity in today's SoC designs, the importance of design reuse, verification, and debug becomes inescapable. SystemVerilog [1], VHDL [2], and SystemC [3] have unique strengths which make them more suitable to certain application domains. Mixed-language designs are proliferating because designers want use the powerful features of one language for creating test benches for designs written in the other language. Diversity of design teams with their different preferences, and integrating a growing number of IP blocks in a SoC, often written in different languages, also leads to a mixed-language scenario.
DVCon 2010
34604
The OVM-VMM Interoperability
Featured Paper by Tom Fitzpatrick & Adam Erickson

The Accellera Verification IP Technical Subcommittee (VIP-TSC) has spent the past year-and-a-half developing an interoperability class library to allow OVM- and VMM1-based VIP to work together in a single environment. This paper will describe the primary obstacles we encountered while bridging these two independentlydeveloped methodologies.
DVCon 2010
34616
A Holistic View of Mixed-Language
Featured Paper by Pankaj Singh & Gaurav Kumar Verma

IP reuse has long been touted as one of the key factors in enabling development of today’s complex SoC designs. The concept of reuse seems simple and easy in theory, but there are a number of obstacles that design and verification teams must address to be successful, especially in the case of commercial IP cores. One of the significant barriers to IP reuse today is the wide variety of design languages used in IP.
DVCon 2010
35578
90nm Migration
8 analog mixed signal IP modules including ADCs, DACs, PLLs, bandgaps. IN2FAB Technology
35820
Design Flow
Today's complex designs, especially those targeted to deep submicron technologies, demand a good methodology at all stages of the design cycle in order to meet the quick turnaround requirements of customers. QualCore Logic, Inc.
38418
Continuous Glucose Measurement
ASIC development by ZMDI of an implant for continuous glucose measurement. Whitepaper published in MEDIZEN+elektronik Magazine (01/2013) ZMDI
38693
Modeling, Simulation,
Featured Paper by A.K. Piłat

Introduction: The dual electromagnet configuration of Active Magnetic Levitation system (AML) where the electromagnets are locate opposite to each other, constitutes and single axis of the Active Magnetic Bearing. The same configuration can be used to test the single electromagnet AML controller. A single electromagnet AML was modeled and simulated with COMSOL Multiphysics. The modeling and simulation of the AML configuration is required when a new devices are designed or existing one are modeled for the verification and controller synthesis purposes. In both cases there is a request to add the control feedback to keep the levitated object at the desired position. Therefore, the model must be extended with the motion dynamics and controller formula. Such models are also useful for educational purposes to demonstrate interdisciplinary aspects of modeling, simulation and control. Use of COMSOL Multiphysics: Modeling with support of COMSOL Multiphysics is well suitable for educational and research purposes.
Comsol
38935
A Multiphysics Approach
The magnetrons used in microwave ovens operate on the same frequency band as Wi-Fi equipment, and the radiation they release can interfere with the operation of wireless networks. This paper presents a multiphysics simulation of a magnetron using CST STUDIO SUITE®, with the aim of testing the electrical, magnetic, thermal and mechanical characteristics of a low-interference magnetron design. The simulation results are then compared to measurements made experimentally, and the two sets of results are shown to be in good agreement. CST - Computer Simulation Technology
30585
Advanced modeling methodology
This test case, based upon a SEU soft-error application, demonstrates the power of InfiniScale’s methodology. InfiniScale®
30695
winIDEA Software
winIDEA - Integrated Development Environment Advanced iSYSTEM AG
33389
Using Formal Verification
Chip designers worldwide have told us that Jasper is fundamentally different in how we approach their technical and business problems by delivering a high ROI (return on investment) through the application of advanced formal verification techniques. Our tools address a spectrum of key verification challenges – from getting the architecture unambiguously right, to putting more power in the hands of designers, to promoting design reuse, to verifying critical functionality, to reducing process bottleneck, and even silicon debug. Jasper Design Automation
33980
PCB Layout
What is PCB Layout? * PCB Layout is the process of creating the artwork necessary to manufacture a printed circuit board *PCB board design defines the electrical pathways between components 911EDA, Inc.
34158
Bluetooth 3.0 + HS - Features
This presentation/whitepaper is targeted for developers who already have an understanding of the Bluetooth technology and who would like to get a quick understanding of the new features introduced in Bluetooth 3.0 + High Speed version of Bluetooth Specification. Wipro Technologies
34286
Transistor Level Gate
Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly more difficult to represent as simple ramps due to highly resistive interconnects and Miller cap effects at receiver gates. CLK Design Automation
34302
Company Brochure
Our abilities encompass a wide variety of skills, commencing with the initial design and innovation of a product and culminating in the ongoing manufacture of a complete product or assembly. These turnkey solutions are individually tailored and are designed around each customer’s specific requirements. Contract Electronics Manufacturing Services: Kingfield Electronics UK
34421
Power Architecture evaluation
Cosmic tools for Power Architecure family, evaluation version limited to 8k. Cosmic Software
34441
Controlling Source Code
Software developers today face significant opportunities and challenges. The appetite that both organizations and consumers share for software has made development a dynamic and competitive business, creating opportunities for large companies and start-ups alike. Coverity, Inc.
34466
Finding Reset Nondeterminism
Due to increases in design complexity, routing a reset signal to all registers is becoming more difficult. One way to solve this problem is to reset only certain registers and rely on a software initialization sequence to reset other registers. This approach, however, may allow unknown values (also called Xvalues) in uninitialized registers to leak to other registers, leaving the design in a nondeterministic state. Although logic simulation can find some X-problems, it is not accurate and may miss bugs. A recent approach based on symbolic simulation can handle Xs accurately; however, it is not scalable. In this work we analyze the characteristics of X-problems and propose a methodology that leverages the accuracy of formal X-analysis and can scale to large designs. This is achieved by our novel partitioning techniques and the intelligent use of waveforms as stimulus. We applied our methodology to an industrial design and successfully identified several Xs unknown to the designers, including three real bugs, demonstrating the effectiveness of our approach. Avery Design Systems, Inc
34911
Derating of Schottky Diodes
Schottky diodes use a metal-semiconductor junction as opposed to the semiconductor-semiconductor junctions used in standard diodes. This configuration allows for lower forward bias voltage drops (0.15V - 0.45V vs. 0.5-0.7V) and faster switching times, making them ideal for power supply switching operations. Drawbacks for schottky diodes include much higher reverse bias leakage current ratings. Because p-n recombination is not a factor in switching delay time, only capacitance affects the reverse switching time. DfR Solutions
34969
Next Generation Mobile Devices
The mobile phone is already becoming the most ubiquitous digital device across the world, and promises to reach two thirds of the world population by the end of this decade. Sasken (Formerly Silicon Automation Systems Inc.)
34972
Can 3G technologies benefits
G Venkatesh | Exec. Director & Corp. CTO/CSO, Sasken Ashwin Ramachandra | Product Architect, Sasken Sasken (Formerly Silicon Automation Systems Inc.)
34985
Verification of H.264
H.264 high and baseline profile codec systems are implemented on Virtex-5 multi- FPGA board. The codec supports full HD class video and the FPGA board called iNEXT consists of up to four 33-million FPGA. Dynalith
35297
Migrating to UVM: how and why!
Motivation – Why do we need a common methodology? – What should a methodology provide? Test and Verification Solutions
35418
Design for Testability
Even in the very early days of electronic components failures appeared. Despite enormous development and production improvements this situation has not changed. Even automated equipment faults continue to be created on circuit boards There is not a single manufacturing technique that will guarantee the 100 percent fault free circuit board. Each new technology creates new challenges and test methodologies to ensure fault free boards. GÖPEL electronic GmbH
35466
Using Multicore Processors
Many of the developments in silicon, software and development tools that embedded engineers use today first appeared in disciplines other than embedded computing, and have been adopted and adapted from these other disciplines to meet the requirements of embedded projects. For example, the C-language was developed at Bell Labs for implementing system software on Unix machines, and GUIs found their first applications in gaming machines and PCs. Hitex Development Tools
35567
Using Cost-Effective
Applications for non-volatile memory (NVM) encompass a wide range of programming requirements. Some products require one-time programmable (OTP) memory that is programmed during chip fabrication – mask ROM is good for this purpose if the code is frozen. Other products need field-programmable OTP for applications such as analog trimming, necessitating the use of secure in-system programmable NVM. Sidense Corporation
35584
Adapting AMI to Support
Proposed approach to increase the accuracy of channel simulations by including back-channel communications. The IBIS AMI modeling standard can be readily extended to support the new approach. This expands on the presentation given at the IBIS meeting in February, 2011. Related Sigrity products: SystemSI - Serial Link Analysis. SIGRITY, Inc.
35615
Simbeor Screen-Casts
S-parameters quality assurance and macro-modeling automation with Touchstone Analyzer tool in Simbeor Simberian Inc.
35701
BSIM3v3.1 Model Parameter
BSIM3 was developed in an effort to solve the problems of semiempirical models and as a complement to BSIM 1-2. It has extensive built-in dependencies of important dimensional and process parameters such as channel length, width, gate oxide thickness, junction depth, doping concentration, and so on. The MOSIS Service
35810
XJTAG boundary scan maximises
6TL Engineering, headquartered close to Barcelona, Spain, producesmodular test platforms that fast-track development of customised electronic production test equipment. The platforms save specialist integrators and in-house test-engineering teams from spending time and effort to implement core functionalities such as control processing, power supplies, instrumentation and commonly used test functionality. Standardised interfaces allow customers to connect their own test fixtures and add specific test capabilities quickly and easily using 19-inch rack modules or, optionally, PXI modules. XJTAG
38583
Calculations of the FMR
Featured Paper by M. Mruczkiewicz, M. Krawczyk, V.K. Sakharov, Yu. V. Khivintsev, Yu. A. Filimonov & S. A. Nikitov

FMR spectra of the periodic microstructures (one-dimensional magnonic crystals, 1D MCs) were obtained using COMSOL with use partial differential equation interface. Results of these calculations were successfully compared with an experimental data for Damon-Eshbach (DE) and Backward-Volume (BV) geometries. The presented tool allows to analyze periodic structures with various geometries and material parameter compositions, being at the same time a tool that can serve for optimization and tuning the absorption of electromagnetic waves in ferromagnetic materials.
Comsol
38615
Computation of Capacitance,
Featured Paper by S.M. Musa, M.N.O. Sadiku & J.D. Oliver

In this paper an attempt has been made to design and analyze integrated circuit interconnects for unshielded four conductors with three levels system using Finite Element Method (FEM). The computational and simulation work has been carried out with help of COMSOL Multiphysics software. We illustrate that FEM is as accurate and effective for modeling multilayered multiconductor transmission lines in strongly inhomogeneous media. We mainly focus on designing of two electrostatic models of unshielded four interconnected lines with three levels system. We computed the capacitance and inductance matrices for these configurations.
Comsol
38729
VLSI Layout Based Design
Featured Paper by R. Komaragiri, Sarath. S. & N. Kattabomman

This paper focuses on the diaphragm design and optimization of a piezoresistive Micro Electro Mechanical System (MEMS) pressure sensor by considering Very Large Scale Integration (VLSI) layout schemes. The aim of these studies is to find an optimal diaphragm shape by Finite Element Method (FEM) using COMSOL®, which is most suitable for VLSI layout. Optimal diaphragm shape is a diaphragm shape that results in reasonable output stimuli with minimal deflection and stress. Three different shapes of diaphragms are considered in this study are circular, square and rectangular. Not only form the VLSI layout aspect, but also from the pressure, stress and sensor output considerations, square shaped diaphragms are preferred.
Comsol
39954
SI/PI and EMC/EMI Simulation
CST PCB STUDIO™ is a specialist tool for the investigation of Signal and Power Integrity and the simulation of EMC and EMI effects on PCBs. Regardless of the application type – high speed digital, analog/mixed signal, or power supply – CST PCB STUDIO (CST PCBS) will help you to get it right first time. CST - Computer Simulation Technology
30192
Show Me Next-Generation HDMI
With an install base of over 1.1 billion devices worldwide, HDMI has become the de facto multimedia interface for all digital home and mobile/portable multimedia devices. The recently introduced HDMI 1.4 specification further reinforces the HDMI message of performance, reliability and simplicity. Features like the HDMI Ethernet and Audio Return Channel (HEAC), introduced in version 1.4, further simplify digital home theater wiring while adding new and innovative features. In addition, the HDMI 1.4 specification supports advanced media capabilities such as enhanced color spaces for digital still cameras, 3D modes and ultra-high resolution display formats (up to 4x higher than 1080p) that will be key features in the nextgeneration of premium multimedia entertainment consumer electronic products. Synopsys Inc.
30495
EDWin XP 1.71
EDWinXP is a Total Integrated EDA/ECAD Software package of seamlessly integrated, task oriented modules covering all stages of the electronic circuit design process - from capturing the idea of a circuit in the form of schematic diagram to generate a full set of documentation for manufacturing and assembling of PCBs". It is a complete suite that has Schematics Editor, PCB Layout Editor, Fabrication manager, Library manager and many more Visionics
30849
Enhanced Process Reliability
The bank is part of a large European group that was founded more than a century ago. Headquartered in Paris, the group has a presence in more than 60 countries and employs more than 160,000 professionals. The group controls assets over 588 Billion Euros and owns market capital of just under USD 20 Billion. MindTree Ltd.
32217
Formal Methodology Validates
Bugs in RTL code are problematic, but a bug in an architectural specification can be catastrophic. If the bug remains undetected until post-silicon debugging, the design process essentially starts all over again. Jasper Design Automation
33979
New Software Tools Causing
PCB Layout CAD software programs are undergoing dramatic and significant changes as companies release new versions at an increasingly rapid rate. These new versions not only fix bugs, but they add additional features and versatility. 911EDA, Inc.
34275
Data Management for a
• Involves geographically distributed teams with project lasting over several years • Project goes through different design phases with more designers joining the project • EDA tool skill level/understanding of DM concepts varies amongst designers Cliosoft, Inc.
34303
Company Brochure
Our abilities encompass a wide variety of skills, commencing with the initial design and innovation of a product and culminating in the ongoing manufacture of a complete product or assembly. These turnkey solutions are individually tailored and are designed around each customer’s specific requirements. Contract Electronics Manufacturing Services: Kingfield Electronics UK
34310
Boundary-Scan Parallel
The market for voice over IP (VoIP) products is one of the fastest growing and fastest evolving markets in the high-tech world. Enterprise level VoIP is expected to grow 20% annually through 2009, according to The Insight Research Group. To stay on the leading edge, companies like Zultys Technologies must emphasize short time-to-market, lowered costs, and superior quality. Corelis
34456
Using Static Functional
This paper presents a study of verifying a memory controller using a static functional verification tool. Static functional verification is a new technology that does not use vectors or dynamic simulation but analyses the behaviors of a design by the use of a property language. This paper presents the design and verification challenges of a controller, and how static verification was used to debug the design, what improvements were seen in methodology, and what was achieved and learned by using a static tool. Averant
34457
An Introduction To Property
The increasing complexity of system-on-a-chip and ASIC designs has caused an ever-widening gap between what can be designed and what can be. It is estimated that between 50-70% of the time required to design a complex IC is spent in verifying that the functionality of the system is correct. Bugs in a design are least expensive to fix just after they are created. At this stage the design is still fresh in the designer's mind and other parts of the project or other design team members are unaffected. Bugs are at least an order of magnitude more expensive to fix during system integration. In this phase it takes more time and people to analyse the cause, regression tests must be rerun, and the entire group may be delayed. These challenges are giving rise to some exciting new tools and approaches in Verification techniques. Averant
34459
Solving Verilog "X" issues
Paper by Mike Turpin of ARM, Ltd., describing how to use Solidify for Sequential Equivalence check in order to uncover hidden "X" values in a design. This is particularly important for an IP provider where the RTL may be implemented using different synthesis flows. Hidden X's can cause differences between RTL simulation and the actual silicon, which are not caught by design flows that rely on other tools such as Logical Equivalence checking. Averant
34462
A Guided Tour of SimCluster
SimCluster is an innovative parallel, distributed simulation environment that provides a scalable, open, and flexible solution to increase RTL and gate-level simulation performance and capacity by 300-700% or more. SimCluster supports Verilog and VHDL design methodologies and the most popular simulators (NCVerilog, Verilog-XL, VCS, and ModelSim), hardware accelerators, and emulators. Avery Design Systems, Inc
34521
Towards Provable Protocol
Featured Paper by Jens E. Becker, Oliver Sander, Alexander Klimm, J¨urgen Becker, Katharina Weinbergery, Slava Bulachy & Robert Bosch



Serial communication protocols are the backbone in today’s automotive electric/electronic-architectures. Protocol conformance is of paramount importance to ensure interoperability, error free and reliable communication of electronic control units.
DVCon 2011
34582
Complete NAND Flash Solution:
NAND FLASH memories are non-volatile, inexpensive and of high capacity. These characteristics make these devices ideal for fulfilling the storage requirements in the exploding mobile device market. Designers using NAND FLASH devices should follow the ONFI standard interface to ensure that their controller design will operate with devices from any vendor. The memories need both digital and analog interfaces between the devices and the system they serve. When designers add NAND devices to the system design they must consider the least expensive and lowest risk means of implementing the controller. Arasan Chip Systems
34590
Apples versus Apples
Featured Paper by Brett Lammers & Riccardo Oddone

Over the past few years the discussion of hardware verification languages (HVLs) has come full circle. At first, verification teams tried to assess the strengths and weaknesses of individual language features with the goal of creating their own verification libraries and environments but generally without the context of a reuse methodology. As these groups became more sophisticated and sought to exchange and reuse verification IP (VIP), they coalesced on the two IEEE standardized verification languages – 1800 SystemVerilog and 1647 e and moved toward the industry supported methodologies and libraries built with these languages. With the advent of a single methodology implemented in both languages – OVM multi-language – the discussion has returned to HVL features but now that the reuse methodology known, a clear apples versus apples comparison is now truly possible.
DVCon 2010
34603
An Experience of Complex
Featured Paper by Sabih Agbaria, Dan Carmi, Orly Cohen, Dmitry Korchemny, Michael Lifshits, & Alexander Nadel

There are two main techniques used for RTL validation: simula- tion and formal verification. The main drawback of simulation is its inability to provide satisfactory design coverage when the num- ber of important scenarios is very large. Formal verification pro- vides exhaustive coverage, but its capacity is insufficient for realis- tic designs.
DVCon 2010
34608
Mixed Signal Verification
Featured Paper by Neyaz Khan

Virtually all modern SoC designs today are mixed-signal in nature. Most systems have to interface their millions of gates, DSPs, memories, and processors to the real world through a display, an antenna, a sensor, a cable or an RF interface. The already complex task of functional verification at the SoC level is getting harder and more time consuming. Up until recently, mixed-signal designs could be decomposed into separate analog and digital functions.
DVCon 2010
35328
Emulation: Enabling Hardware/Software
Each DAC, we see a wealth of verification products proposed by those EDA companies exhibiting at the conference. All promise to solve the ever increasing time-to-market pressures, the escalating integration of embedded software and high-performance imposed on electronic products. EVE USA Inc.
35330
Get Faster Verification
We have numerous ways of expressing our skepticism when it looks like we can get something for nothing. There’s always a price to pay. EVE USA Inc.
35355
Measuring Real-Time Performance
Thread-Metric is a free benchmark suite designed to measure the performance of an RTOS. It can be adapted to measure any RTOS, enabling performance comparison to assist in RTOS evaluation and selection. Links below provide a presentation that describes the Thread-Metric suite, and the code itself. Express Logic, Inc
35356
Managing Energy Savings
The use of power-aware MCU features along with poweraware software and development tools can lead to significant optimization of low power consumption. Express Logic, Inc
35410
Mobile Tranceiver
A mobile transceiver chip was designed by a fabless IC company and built on a SiGe BiCMOS process. The chip functioned properly in most aspects, except that it fell short of the RF power output specification. So the analog and RF design team rushed to debug and correct the problem. Gradient Design Automation Inc.
35413
New Methodology on Electro-Thermal
This paper presents a new methodology to characterize and simulate the electro-thermal aspects of packaged power drivers using lateral bipolars. Maximum elevation of junction temperature due to the electrical power stress is sensed in the field of the drivers. Those measurements are further complemented by the transient interferometric mapping (TIM) inspection. Gradient Design Automation Inc.
35414
Already scanned today?
Since its standardisation as IEEE 1149.1 in 1990, JTAG / Boundary Scan has developed to one of the most important technology within the ensemble of various test strategies. This topic’s high dynamics and practical relevance are marked by constantly new operation fields, system solutions and definitions of pursuing IEEE standards. GÖPEL electronic GmbH
35451
Embedded File Systems
Embedded File Systems Add Reliability to Data Management on Flash Micros HCC-Embedded
35465
Using Multicore Processors
In the previous article we saw how traditional methods of increasing the performance of computer systems are reaching a plateau, while the advent of multicore processors has brought the seemingly impossible prospect of ever‐increasing performance without excessive increases in power consumption. Hitex Development Tools
35508
Testing Multicore Software
Hardware verification engineers have always faced the complexity of concurrent execution and temporal considerations when verifying hardware designs. However, silicon manufacturers are now moving to multicore designs (i.e. multiple CPU cores on a single chip) to achieve the relentless drive for improved performance at lower power now demanded by consumers. Test and Verification Solutions Limited
35580
High-Speed, Real-Time
Delivering advanced system solutions since 1988, Signatec is a leading designer and manufacturer of high-speed, PC-based data acquisition, parallel and FPGA digital signal processing, continuous signal data recording and arbitrary signal generation systems. Signatec differentiates itself by being one of the only single-source suppliers that works with its customers to build affordable, real-time signal technology systems for advanced radar, SIGINT, ultrasound, imaging and other high-speed communications systems. Signatec, Inc.
35596
High Definition Video
Oliver Vellacott, IndigoVision CEO, explains that the latest low bandwidth High-Definition IP cameras will accelerate the move of HD into mainstream surveillance applications. IndigoVision Inc.
35604
Efficient model-based
This paper aims at presenting a new model-based flow targeting analog/RF circuits sizing with significant improvements of parametric yield at a very early stage in the design phase. The flow is then applied on a ST Microelectronics [2] LDO regulator design. In a first step, the regulator is modeled. In the second one, the design is optimally sized. The process parameters are then modeled, and finally the sensitivity of the design to the process is analyzed. InfiniScale®
35614
AWR® iFilter™ Application
Like all RF and microwave components, a differential fi lter design will remain only a simulation exercise if it is not created with its manufacturing process in mind. That is, the tight dimensional tolerances required to meet a set of performance goals must be within the capabilities of the fi lter’s manufacturing process in order to realize a reliable, repeatable fi ler. AWR Corporation
35616
Interconnect Design Exploration
Interconnect Design Exploration in Simbeor 2011 (geometry synthesis, network editor, macro-modeling) Simberian Inc.
35718
Soft IP for the Analog
Although all real engineers would like to create all of their designs from scratch, that just is not practical in today’s fast-paced ASIC development world. The need to integrate intellectual property (IP) from third-party providers is the reality. Triad Semiconductor
35814
Building Zero Latency
ESO is the intergovernmental science and technology organisation in astronomy. It is carrying out an ambitious programme focussed on the design, construction and operation of powerful ground-based observing facilities for astronomy to enable important scientific discoveries. Nallatech Inc
35815
Nallatech In-Socket FPGA
In contrast to accelerator devices that attach to an expansion bus, the new generation of computing devices based on field-programmable gate arrays (FPGAs) sits in processor sockets and has the same access to system memory as a CPU. Nallatech Inc
35910
DFM Tips & Tricks II
Even a single sided a board can be viewed from above or below. Clearly marking all layers with right reading text will enable the board manufacturer to verify the proper orientation for your board. The more layers that are employed to make a board, the more important this becomes. Omni Graphics Ltd.
35935
Achieving Optimal Performance
Cadence Virtuoso is one of most popular applications used by engineers in the semiconductor industry for completing various tasks related to a chip design project. This document provide instructions on how to better optimize Exceed onDemand to maximize the performance benefit. Open Text Connectivity Solutions Group
36180
A Pappajohn Company
A GC Construction Manager in Connecticut and New York reduced overhead costs by 15% with Chameleon, another solution from Construction Imaging. “Chameleon has also helped us take advantage of payment discounts. We know which manager has an invoice at all times and can remind them if a discount is available.” Construction Imaging Systems
37062
Designing affordable,
Texas Instruments (TI) leading power line communications (PLC) technology has enabled Cygnus Electronics to create a PLC hardware and software platform designed for automotive qualification in electric vehicles. Auto-rem implements the Society of Automotive Engineers’ (SAE) J2931-3 specification, which is a narrowband orthogonal frequency division multiplexing (OFDM) proposal for plug-in electric vehicle (PEV) to electric vehicle service equipment (EVSE) communications during PEV battery charging. Texas Instruments
37783
The Second Life of Data:
Written by Gregg Oetting, this technical paper highlights the expectations and challenges of data translation and the importance of model repair and validation. Based on a broad suite of test results, this paper can be an invaluable tool in customer engagements to help highlight the true cost of low quality translation. Spatial
38630
FEM Modeling of Electric
Featured Paper by M. Alsharif, P. Wallace, D. Hepburn & C. Zhou

Failure in cable insulation is generally preceded by a degradation phase that may last several years. A significant cause of cable system failures is the breakdown of electrical insulation between the electrodes. The operational stresses that occur in cable insulation which include thermal, mechanical and electrical effects will vary with time and can cause degradation due to the resulting physical and chemical changes in cable properties. It is widely recognized, irrespective of the causative mechanism, that degradation results in partial discharges (PDs) being generated at the degradation site(s). PDs are small electrical discharges produced by local enhancement of the electrical stress due to conditions around the fault. The internal discharge in insulation material and/or at its interface is caused by the strong and inhomogeneous electrical fields that are usually caused by voids, bubbles, or defects. Treeing discharge is also associated with internal discharge, and it starts from conducting particles or a void in solid insulation. This paper investigates the electric stress within an armoured XLPE insulated cable containing a void-defect. The finite element model of the performance of an armoured XLPE MV underground cable containing void-defect is developed using the COMSOL multiphysics. Use of COMSOL Multiphysics (Electrostatic model): a two-dimensional model of a single-core Cross-Linked Polyethylene (XLPE) cable containing a void-defect has been developed using the COMSOL multi-physics environment. The electrical field distribution in a typical cable construction, is described by a two-dimensional field model. The model is solved for a non-degraded system configuration as a base for further analysis. In addition, an air-filled void is introduced into the model cable insulation to investigate the effect of void presence on the XLPE electrical field insulation system.
Comsol
38634
Design of a Stealth Antenna
Featured Paper by F. De Vita, S. Di Marco, F. Costa & P. Turchi

This paper will describe some applications of COMSOL Multiphysics to the analysis of Frequency Selective Surface (FSS) structures. Particular attention will be devoted to the possibility of designing a stealthy antenna using the FSS structure. In fact, since it possesses a dual filter concept of frequency and polarization for electromagnetic wave, the Radar Cross Section (RCS) of the antenna is reduced.
Comsol
38641
EM Simulation of a Low-Pass
Featured Paper by J.E. Rayas-Sánchez, J. Aguilar-Torrentera, Z. Brito-Brito, J.C. Cervantes-González & C.A. López

We perform EM simulations of a low-pass microstrip filter consisting of a cross-junction open stub and t