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Solving Engineering File
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Understanding Grounding
Misunderstanding how ground is implemented in circuit simulation is one of the most common misuses of electromagnetic (EM) simulators and their results. This white paper discusses the defi nition of ground in EM simulators and how to correctly choose among various grounding options, a topic of special importance to designers using the results in a circuit simulator. Many modern simulators now support the notion of local grounding, where different ports can use different ground defi nitions. New features in AWR’s AXIEM™ 2009 3D planar EM simulator offer extensive sources/ports and de-embedding options, including internal edge, fi nite difference/gap and extraction ports, and per-port, coupled line and mutual group de-embedding. AWR Corporation
A Plethora of Ports:
Electromagnetic (EM) simulation technology software has come a long way since it first became popular for microwave and RF circuit design back in the 1980s. With the sophistication of today’s EM tools, it is sometimes difficult to remember how limited those early simulators were. The author is old enough to remember when a challenging problem for a 3D planar simulator consisted of a coupled-line filter with 1000 unknowns and 3D finite element simulators were stressed by a simple multi-layer via transition in a package. AWR Corporation
A Basic Mathematical
Electronic Design Automation (EDA) has been one of the great enabling technologies for modern electronics, including the class of analog circuits classified by their operating frequencies: RF/wireless, microwave, millimeter-wave, etc. Initially distinct and discrete software tools were developed for (logical) circuit simulation and (physical) layout, and these were later augmented by physical verification (DRC & LVS), system simulation, and electromagnetic analysis (EM). Later still, all of these tools came together under unifying environments providing a common database and standardized graphical (schematic) entry. AWR Corporation
High-Speed Serial Backplane
The benefit to having high-frequency design tools resident on a Vector Network Analyzer (VNA) does not become obvious until the time comes to compare simulation to measurements. At this point, the advantage of a more streamlined work flow -- without the impediment of transferring data to a simulator running on a separate PC or workstation - becomes clear. To illustrate the benefit of such a novel, integrated solution (AWR’s Microwave Office software “inside” the Anritsu VectorStar VNA), this application note follows the design flow for a high-speed serial backplane. AWR Corporation
Clock and Reset Ubiquity:
Today’s SoC integrates a collection of peripherals, memory, graphics, networking and I/O components that originate from a multitude of sources. It could comprise designs from within the company, from other companies or from third-party IP vendors. These independently developed components come together to enable a rich feature set for the SoC. However, accompanying this abundance of features is a significant amount of complexity that needs to be correctly and efficiently handled to render the integration successful. One such source of complexity is that components operate at clock frequency ranges that may be very different from those of their counterparts. The existence of these multiple clock domains and the need for them to exchange information creates a hotbed for CDC bugs to thrive. As a result, CDC verification becomes critical to ensure that metastability is not introduced in the design. In this article, we provide several situations with varying set of examples that showcase the challenges in CDC verification. Real Intent, Inc.
Design Flow for Base
Automated synthesis of microwave devices has been gaining in popularity in CAE applications over the past decade. Antenna Magus now brings this capability to the fi eld of antenna design. Antenna Magus provides a structured catalog of antennas (monitor image below) with concise documentation, robust design algorithms, and export models. AWR Corporation
Design and Synthesis
Next generation high power, high and width electronic devices rely on well-designed RF/microwave components for peak performance. In the specialized world of RF and microwave engineering, the design and development of power amplifi ers (PAs) is a specialty within a specialty that requires many years of focused engineering experience and a suitable collection of test and measurement (T&M) equipment. AWR Corporation
High-Power Amplifier
SYMMIC from CapeSym is a template-based thermal simulator that has been optimized for monolithic microwave integrated circuit (MMIC) design. This application note demonstrates the integration of Microwave Office and SYMMIC. The integration is script-based and requires minimum manual ntervention as compared to non-integrated thermal solvers. The example used here is an extension of the MMIC high power amplifier (HPA) example that is part of the standard Microwave Office set of examples. AWR Corporation
Design and Optimization
3D electromagnetic (EM) simulators are commonly used to help design board-to-chip transitions. AWR now makes life easier for circuit designers with the introduction of Analyst, a full featured, 3D EM fi nite element method (FEM) simulator. The key advantage of Analyst over other available 3D simulators is its tight integration within the Microwave Offi ce® design environment, AWR’s circuit design and simulation platform. This application note highlights the unique features of Analyst by demonstrating the optimization of the transition from a board-to- -chip signal path. The example shows how the ability to access Analyst from within in the Microwave Offi ce environment saves designers time and provides ready access to powerful layout and simulation tools that are not available in typical circuit design tools. AWR Corporation
AWR's Support of Polyharmonic
Linear and nonlinear device models are the building blocks of most RF and microwave designs. S-parameters are often used to represent linear devices. As a “black-box” model, they can easily be obtained using a vector network analyzer and distributed for simulation. S-parameters use superposition to equate the linear relationship between incident and refl ected waves at all of the device’s ports. Nonlinear devices, however, distort waveforms such that their behavior cannot be represented through superposition or S-parameters. AWR Corporation
Synthesizing & Optimizing
Like all RF and microwave components, a distributed filter design will remain only a simulation exercise if it is not created with its manufacturing process in mind. That is, the tight dimensional tolerances required to meet a set of performance goals must be within the capabilities of the filter’s manufacturing process in order to realize a reliable, repeatable filer AWR Corporation
End-to-end Design and
The X-band frequency range has been designated for critical military and public safety applications such as satellite communications, radar, terrestrial communications and networking, and space communications. It is important to ensure that these signals deliver quality, reliable, and secure communications. This application note describes the design and realization of a complex X-band transmission analyzer for use in real-time material testing. AWR Corporation
Leverage Circuit Envelope
Moving to next-generation cellular systems requires new levels of performance from RF power amplifiers (PAs). While designing PAs has always included the challenge of maximizing efficiency while delivering high linearity, never have the tradeoffs been so difficult as they are for 4G/LTE. For instance, the latest higher-order modulation schemes require exceptional linearity throughout both transmit and receive signal paths, yet wireless carriers demand the highest possible efficiency at the system level. AWR Corporation
Exactly How EM Should
Modern RF/microwave design flows make extensive use of electromagnetic (EM) analysis in many ways, and its co-existence and concurrency with circuit design and analysis can not be underestimated. Prior to the circuit design and especially in larger designs, EM tools are used to create “library” parts such as inductors, transitions, and antennas. While these parts are fairly self-contained, they must ultimately be integrated into the overall design where at the very least they must be connected to the rest of the circuit or in a more complex case be coupled to it. During both early and later stages of design, designers will switch from circuit-based models to EM analysis of critical interconnects to better understand couplings and achieve greater accuracy. EM analysis is used again before the design goes to manufacturing, so that the metal in the design can be analyzed one more time to verify circuit performance alongside design rule check (DRC ), layout versus schematic (LVS), and even design for manufacturability. AWR Corporation
Understanding and Correctly
Understanding and correctly predicting cellular, radar, or satellite RF link performance early in the design cycle has become a key element in product success. The requirements of today’s complex, high performance wireless devices are driving designers to assess critical measurements—noise fi gure (NF), 1dB gain compression (P1dB), third order intermodulation distortion versus output power (IM3dBc), and signal-to-noise ratio (SNR)—long before manufacturing begins. Traditional modeling methods such as rules of thumb and spreadsheet calculations (Friis equations) give limited insight on the full performance of an RF link in next-generation wireless products. AWR Corporation
ACE - Automated Circuit
The Traditional approach to RF/MW circuit design – which is the present day foundation for high-frequency wireless design applications – is being pressured simultaneously by an increase in operating frequencies / bandwidth and a decrease in physical footprint size. The result is that the physical design challenges faced by circuit designers are rapidly increasing, while choices for how these challenges should be best-addressed are not. AWR Corporation
Understanding Available
RF system-in-package (SiP) and multi-chip-module (MCM) designs present engineers with the challenge of integrating complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) for digital circuits and gallium arsenide (GaAs) or silicon germanium (SiGe) devices for RF and microwave circuits with soft-board laminates and low-temperature co-fi red ceramic (LTCC) packages. Software used to design these complex circuits must seamlessly bring together synthesis, simulation, and verifi cation solutions via a single interface in order to ensure optimum component design and placement in each technology. It must also construct schematics and perform physical design entry for any technology in the SiP using uniform commands and menu options. AWR Corporation
The Advantages of Multi-rate
Harmonic balance (HB) analysis is a method used to calculate the nonlinear, steady-state frequency response of electrical circuits. It is extremely well-suited for designs in which transient simulation methods prove acceptable, such as dispersive transmission lines in which circuit time constants are large compared to the period of the simulation frequency, as well as for circuits that have a large number of reactive components. In particular, harmonic balance analysis works extremely well for microwave circuits that are excited with sinusoidal signals, such as mixers and power amplifiers. AWR Corporation
Design of a Near Field
Near field communication (NFC) is being developed as a form of contactless communication between wireless devices like smartphones and tablets. This technology enables users to do things like swipe their devices at the checkout stand or wave them over another NFC-compatible device to share information instantly without complicated setups or physical connections. AWR Corporation
Steady State and Transient
Thermal effects in electronic devices are studied to investigate their influence on reliability and electrical performance. Due to the decreasing size of semiconductor devices operating at unchanged power levels, thermal analyses provide circuit designers with important information about device degradation and electro-thermal coupling. Steady state thermal analyses have been performed for many years in electronics reliability engineering to evaluate device lifetimes. Device channel temperature is the most critical parameter to determine in such a reliability study as it is the primary source for thermal degradation mechanisms. Many techniques exist for modeling and measuring device channel temperatures, however large discrepancies are reported in the literature [1]. AWR Corporation
Upfront RF Planning Speeds
High-frequency technology didn’t earn its reputation as black magic for no reason. Unlike low-frequency circuits, microwave circuits don’t behave in a totally predictable way, so “tweaking” has been an accepted mainstay of the microwave design approach/fl ow. Fortunately, high-frequency design tools have dramatically improved so that tweaking of prototype circuits is much less common, and today’s engineer has powerful tools that can make sense of the black magic. AWR Corporation
Visual System Simulator
Achieving the highest possible performance from circuits used in third-and fourth-generation wireless systems is driving a tighter integration of previously disparate tools. Certainly, a level of software synergy is essential when designing circuits for use in today’s wireless systems that employ higher-order modulation techniques together with advanced technologies, such as Orthogonal Frequency Division Multiplexing (OFDM), multiple-input multiple-output (MIMO) and digital predistortion (DPD) circuits, to name a few. As this white paper illustrates, AWR’s Visual System Simulator (VSS) and National Instruments’ LabVieW graphical programming nvironment are now co-simulating so as to better enable designers to analyze, optimize, and verify complex RF circuits, subsystems and digital signal processing within a unified framework. AWR Corporation
How to Optimize an LTE
Long Term Evolution (LTE) is rapidly being deployed by major US carriers and will serve most, if not all, top-tier markets some time during 2012. LTE is often called a fourth-generation (4G) standard, and provides signifi cantly increased peak data rates, with the potential for 100 Mbps downstream and 30 Mbps upstream, reduced latency, scalable bandwidth capacity, and backwards compatibility with existing Global System for Mobile Communications (GSM) and Universal Mobile Telecommunications System (UMTS) technology. AWR Corporation
Improved Circuit Design
To fi ne-tune an RF/microwave design to meet new design criteria, engineers turn to the built-in optimizers within their electronic design automation (EDA) software. A typical optimization case for a microwave filter, for instance, might include goals for in-band insertion loss and return loss, cutoff frequency, and out-of-band rejection. The large number of criteria that the optimization engine then has to take into consideration to create a landscape of “solutions” are more or less random, and, more often than not, quite large. AWR Corporation
Hardware in the Loop:
When simulating a complete subsystem such as a wireless communication device or radar receiver, the quality of measurement data becomes essential to ensure that the fi nished product meets or exceeds the demands the system will encounter in service. The measurement data can be used to make changes to the system early in the design process, when those changes can be realized in the least amount of time and at the lowest cost. However, this can be accomplished only if there is a direct link between the system being simulated and the measurement equipment itself—that is, when there is “hardware in the loop.”AWR’s Visual System Simulator™ (VSS) combined with its TestWave™ software provides an end-to-end communications system simulation environment that makes this possible. AWR Corporation
Using LabVIEW in the
Many veteran designers no doubt remember how comparatively simple it was to design base station or mobile phone amplifi ers when the only modulation technique was analog and amplifi er performance could be verifi ed using Additive White Gaussian Noise (AWGN). Nowadays, second (and subsequent) generations of wireless networks usher in digital modulation techniques that necessitate the need to stimulate amplifi ers and other circuits with waveforms they actually process in service. It therefore necessitates far tighter integration between the baseband signal processing and high-frequency circuit design tools as well as actual test equipment for both generating these modulated waveforms and evaluating their effects on the performance of the design. AWR Corporation
Matching Network for
One of the most common tasks required of an RF engineer is basic impedance matching. AWR’s Microwave Office® software has included this ability for a long time now via a manual ‘step through’ matching process, however, the latest release of AWR’s Microwave Office now supports the addition of an automated impedance matching wizard, coined iMatch, that allows the user to quickly compare different matching topologies and choose the best solution based upon requirements. AWR Corporation
Using Visual System Simulator
The concept of software defined radio (SDR) has existed for many years. Consequently, you can find many descriptions of an SDR. A concise definition of an SDR is a radio in which some or all of the physical layer functions are software-defined. The physical layer function is the layer within the wireless protocol in which processing of RF, IF, or baseband signals (including channel coding) occurs. Many of today’s SDRs have part of the signal processing implemented in software. AWR Corporation
Integration of Signal
The system supports easy design in cooperation with test and simulation processes using a signal analyzer/vector signal generator, as well as effective optimization of RF components and overall system performance. Using simulation based on actual measurement data reduces the amount of design and prototyping work, cutting R&D time and costs. Moreover, it can help match performance to requirements, preventing over-specification waste and cutting product costs. AWR Corporation
End-To-End System Design:
Architectural tools used by designers of RF and microwave communications systems include budget simulators, spur searching utilities, and frequency planning tools, all of which are often based on spreadsheets or hard-coded algorithms with a non-commercial user interface. Having served designers well, these “home brew” approaches are limited in functionality and/or breadth, unsupported, and are as varied as the designers who create them. While the level of effort to create these tools was great and once acceptable (if only because there was no suitable alternative), few designers today have the time required to build their own design utilities nor massage existing legacy ones to meet growing requirements of today’s communciation systems. This white paper outlines the benefi ts of using a commercial, specialized software program, such as AWR’s Visual System Simulator™ (VSS) software for end-to-end system design, while also embracing legacy approaches with the incorporation of spreadsheet views. AWR Corporation
Challenges in Verification
Emerging systems have three dimensions of complexity when it comes to making them CDC-safe. First, the number of asynchronous clock domains in designs can range from the tens to the hundreds for complex systems with many components. Second, the master clock frequencies vary per component. It is not uncommon for the ratio between the fastest and the slowest clocks to be greater than 10. Third, the clock frequencies themselves can change dynamically during the course of chip operation to save power. As a result, CDC verification becomes critical to ensure that metastability is not introduced in the design.

This article provides several situations with varying set of examples that showcase the challenges in CDC verification.
Real Intent, Inc.
WAFERMAP is a scientific software to collect, edit, analyze and visualize measured physical parameters on semiconductor wafers. BOIN Scientific Software
TCAD Tools
TCAD Tools N/A
Reduce Verification Complexity
Verification requirements are growing in all market segments. Ensuring these requirements are met requires design verification that goes beyond traditional design rule checking (DRC), layout vs. schematic (LVS) comparison, and electrical rule checking (ERC). Small and large process nodes alike are affected by these requirements, while both system-on-chip (SoC) and full custom designs also need comprehensive reliability coverage.
Learn how Calibre PERC can help you:
  • Understand the interactions between different power domains
  • Ensure signals and voltage domains are protected for all operating conditions
  • Get easy-to-use, unambiguous debug results without exhaustive test vectors
Mentor Graphics
Micro-Cap V
The Micro-Cap V demo is a limited but working version of the main program, an easy to use mixed-mode analog/digital simulator with an integrated schematic editor. Spectrum Software
Voyeur is a visualization tool that displays a circuit schematic on the screen. N/A
BSIM3v3 code and documentation University of California, Berkeley
60nm and 90nm Interconnect
Section 1
-DSM Effects on RF Modeling
- Simple versus Complex Modeling Issues
- Dummy Metal and Slotting Effects -Spiral Inductor Example

Section 2
- DSM Modeling on Interconnects
- Dummy Metal Effects on Delay and Cross-talk for Long Interconnects

Section 3
- Power Delivery Inductance effects on Large Digital IC performance
-Solving RCLK models for VDD and VSS network combined
-Determining the size and placement of on-chip decoupling capacitances
OEA International, Inc.
Power Optimization and
Power Optimization and Synthesis Environment N/A
Sunsite's /pub/Linux/apps/circuits
Sunsite's /pub/Linux/apps/circuits directory Sunsite
A simple yet powerful layout language, BALLISTIC, has been created: high-level layout code can be written for designing automated opamp generators, standard cell layout generators, and other analog integrated circuits.
Multicycle path analysis
By default, a STA tool performs timing calculations based on single clock cycle behavior. There are cases, due to existence of slow logic between flops inside the ASIC/FPGA, where multi clock cycle behavior is required. The best way to explain multicycle behavior is by comparing it against single clock cycle behavior. ASICServe
Nemesis generates tests for stuck-at and bridgeIDDQ faults in combinational circuits, and simulates tests for stuck-at, bridge, and bridgeIDDQ faults in both combinational and sequential circuits. N/A
Verification IP
VIP Synopsys Inc.
Introduction to TimingDesigner
TimingDesigner Movie
(note this movie is 23 minutes long)
EMA Design Automation
HES-7 ASIC Prototyping
Co-authored by: Slawek Grabowski and Zibi Zalewski, Aldec, Inc. & Kirk Saban, Xilinx, Inc.

This paper highlights possibilities of ASIC verification using FPGA-based prototyping, considering the latest Virtex®-7 devices and Aldec HES-7 dual Virtex-7 2000T FPGA ASIC prototyping board. In addition, the most common partitioning issues