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Title : FPGA Design for 10G Ethernet Test Pattern Generator
Company : eInfochips Limited
Date : 02-Jun-2011
Downloads : 1

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The FPGA consists of multiple 1G and 10G Ethernet ports connected to Ethernet switch via XAUI and High speed MGT. Other blocks include PowerPC core, Memory controller and primary to secondary FPGA interface and custom logic for synchronization. The main application of this FPGA based design is to provide an interface to multiple DSPs for uncompressed video-audio transfer via secondary FPGA and to multiple boards via 1G and 10G Ethernet Ports.
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