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DesignCon 2006 Award Papers

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These technical papers are recipients of the DesignCon Paper Award

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Tensilica White Papers

White Papers

 (383)New
White Papers
Title
Company
Added
Automated DRC Waiver Management NewMentor Graphics04-Feb-2010
Combining Low Pin Count Test with Scan Compression Dramatically Reduces Test Interface and Cost NewMentor Graphics04-Feb-2010
ENABLING ASSERTION BASED VERIFICATION NewZocalo Tech12-Jan-2010
Deliver smarter products with requirements engineering. NewIBM21-Dec-2009
Address System-on-Chip Development Challenges with Enterprise Verification Management PopularIBM13-Nov-2009
Automated Assembly and IP Integration Techniques for SoCs Atrenta29-Oct-2009
Verifications of Multi-Clock Design Atrenta29-Oct-2009
Employing Risk Management Techniques to Mitigate Technological and Market Pitfalls -- The Challenges and Realities of High-Performance and Low Power SoC Designs Virage Logic19-Oct-2009
Across the Great Divide… Jasper Design Automation07-Oct-2009
Advanced Schematic-Driven Layout Automation SpringSoft, Inc.07-Oct-2009
Solving Your Top Four Engineering Challenges Open Text02-Oct-2009
The economies of outsourcing Verific Design Automation Inc.02-Oct-2009
3D Modeling and Analysis in EDA Applications Spatial22-Sep-2009
Advanced On-chip-variation Timing Analysis for Nanometer Designs, Part II Incentia17-Sep-2009
Enabling System-level Electrical Co-design for Mixed-Signal Systems PhysWare09-Jul-2009
Challenges and Requirements for Power-Aware Debug SpringSoft, Inc.02-Jul-2009
A Register Transfer Level Approach to Memory Built-in Self Test and Repair Insertion Atrenta16-Jun-2009
A Register Transfer Level Approach to Memory Built-in Self Test and Repair Insertion Atrenta16-Jun-2009
Automated Assembly and IP Integration Techniques for SoCs Atrenta16-Jun-2009
CHALLENGES AND REQUIREMENTS FOR POWER-AWARE DEBUG SpringSoft, Inc.16-Jun-2009
Combining Structural and Functional Verification Techniques to Improve Effective CDC Verification Atrenta16-Jun-2009
Constraints Management: Approach and Techniques for Preserving the Intent of Timing Constraints throughout the Design Flow Atrenta16-Jun-2009
Designing for Test at RTL Atrenta16-Jun-2009
Estimating Fault Coverage from RTL without Fault Simulation Atrenta16-Jun-2009
Facilitating At-speed Test at RTL Atrenta16-Jun-2009
GuideWare™ Atrenta16-Jun-2009
SpyGlass Application in an FPGA to ASIC Conversion Atrenta16-Jun-2009
Interconnect Delay Compensation in Timing Analysis for Designs Containing Multiple Voltage Domains Incentia03-Jun-2009
Physware's Parallelization Methodology PhysWare27-May-2009
The Interpretation of Non-Zero Mutual Resistances in PhysAPEX PhysWare27-May-2009
Data Security in Logic Non-Volatile Memory Technologies Virage Logic20-May-2009
Logic NVM Versus Embedded Flash Technology and Economic Tradeoffs Virage Logic20-May-2009
How to Improve Multisite Design Team Productivity in Uncertain Times Cliosoft, Inc.23-Apr-2009
3D EM Simulation in the Design Flow of High-Speed Multi-Pin Connectors CST-Computer Simulation Technology23-Mar-2009
Comparison of BER Estimation Methods which Account for Crosstalk SiSoft (Signal Integrity Software, Inc.)10-Mar-2009
Accelerating CRCs on eSi-RISC with user-defined instructions NewEnSilica Ltd10-Jan-2010
System Verilog + OVM: Mitigating Verification Challenges & Maximizing Reusability NewAppliedMicro (AMCC)23-Dec-2009
Theory and Best Practice of RSA Compute Offload Processor Design NewCrack Semiconductor19-Dec-2009
Best Paper Award at DesignCon -
A Simple Via Experiment
Popular
SiSoft (Signal Integrity Software, Inc.)25-Feb-2009
SystemVerilog Testbench Debug And Analysis PopularCypress Semiconductor06-Oct-2008
Tutorial: The Changing World of Signal Integrity - Challenges and Solutions PopularAWR Corporation06-Feb-2008
Coding Techniques for Bus Functional Models In Verilog, VHDL, and C++ PopularSynaptiCAD, Inc.14-Dec-2007
Timing (Analysis) is Everything: A How-To Guide for Timing Analysis PopularSynaptiCAD, Inc.14-Dec-2007
Verilog Test Suites PopularVerific Design Automation Inc.06-Oct-2007
Assertion-Based Hardware Debugging - presented at DVCon PopularSpringSoft, Inc.03-Oct-2007
Design and Debug with Advanced Languages: Challenges and Opportunities for SystemVerilog- presented at DVCon PopularSpringSoft, Inc.03-Oct-2007
Resolving EMI Problems with Good Power Delivery Strategy PopularHuawei Technologies16-Aug-2007
Advanced On-chip-variation Timing Analysis for Nanometer Designs PopularIncentia27-Jun-2007
SystemVerilog Assertion Backgrounder PopularSpringSoft, Inc.04-Jan-2007
EDA Survey Results PopularDeutsche Bank F.I.T.T29-Jun-2006
Using Signal Integrity Analysis to Achieve EMC PopularSIGRITY, Inc.13-Apr-2006
A General and Comparative Study of RC(0), RC, RCL and RCLK Modeling of Interconnects and their Impact on the Design of Multi-Giga Hertz Processors. PopularOEA International, Inc.12-Jan-2006
Case Study of On-Chip Inductance Effects (Extraction and Analysis). PopularOEA International, Inc.12-Jan-2006
Transaction-Level Modelling and Debug of SoCs PopularSpringSoft, Inc.03-Jan-2006
CADENCE PHYSICAL VERIFICATION SYSTEM PopularCadence Design Systems, Inc.02-Dec-2005
Ensure valid design constraints throughout the design process PopularCadence Design Systems, Inc.16-Aug-2005
Tools for On-Chip Interconnect Inductance Extraction PopularOEA International, Inc.08-Jul-2005
"60nm and 90nm Interconnect Modeling Chalenges" PopularOEA International, Inc.21-Dec-2004
LTE EPC: Drivers and Bene fits o f Pre-Inte grate d F rame works VERSION RadiSys02-Dec-2009
The Enea System Manager RadiSys02-Dec-2009
Design Philosophy and Methodology Shax Engineering and Systems28-Nov-2009
A Low-Cost Task Specific Solution for IO Pad-Ring and Package Net List Construction SIGRITY, Inc.27-Nov-2009
Trends and Requirements for System-Level Design of Signal and Power Delivery SIGRITY, Inc.27-Nov-2009
Graphical Test Bench Generation SynaptiCAD, Inc.18-Nov-2009
10 Tips for Successful SOC Design Tensilica14-Nov-2009
Cut DSP Development Time – Get High Performance From C, No Assembly Required Tensilica14-Nov-2009
High-Volume nano FPGAs Actel Corporation03-Nov-2009
The formal verification market is still untapped Olivier Coudert22-Oct-2009
Automated low-power design flow is up for grabs Olivier Coudert07-Oct-2009
Verification Intellectual Property (VIP) Best Practices Interoperability Guide. Acellera05-Oct-2009
High-Performance, High-Precision Memory Characterization Altos28-Jul-2009
Small but Deadly : The Life Cycle of an I/O Bug Duolog Technologies10-Jul-2009
Design of ST planar integrated inductors based on INFINISCALE flow InfiniScale®21-Jan-2009
Efficient model-based analog circuits sizing InfiniScale®21-Jan-2009
Process Optimization Ingenuus Software Inc.21-Jan-2009
OSCI TLM2.0 Standard Compliance –Why Bother? Jeda Technologies, Inc.17-Jan-2009
A study of the thermal characterization of a high – performance flip chip package Endicott Interconnect Technologies02-Jan-2009
An Experimental and Computational Study of the Current Carrying Capacity of High Performance PWB Interconnections Endicott Interconnect Technologies02-Jan-2009
Laser Micromachining of Barium Titanate (BaTiO3)-Epoxy Nanocomposite-Based Flexible/Rollable Capacitors: New Approach for Making Library of Capacitors Endicott Interconnect Technologies02-Jan-2009
Resin Coated Copper Capacitive (RC3) Nanocomposites for Multilayer Embedded Capacitors Endicott Interconnect Technologies02-Jan-2009
Addressing 3D Packaging Challenges SIGRITY, Inc.17-Dec-2008
Enabling Predictable Low Power Design and Implementation Cadence Design Systems, Inc.17-Dec-2008
Efficient Noise Analysis for Complex Non-Periodic Analog/RF Blocks Berkeley Design Automation, Inc.12-Dec-2008
A Practical Approach to Preventing Simultaneous Switching Noise and Ground Bounce Problems in IO Rings OEA International, Inc.07-Dec-2008
A dynamic hardware video processing platform Andraka Consulting Group Inc04-Dec-2008
An Onboard Processor and Adaptive Scanning Controller for the Second-Generation Precipitation Radar Andraka Consulting Group Inc04-Dec-2008
Building a High Performance Bit Serial Processor in an FPGA Andraka Consulting Group Inc04-Dec-2008
FIR Filter Fits in an FPGA using a Bit Serial Approach Andraka Consulting Group Inc04-Dec-2008
High Performance Digital Down-Converters for FPGAs Andraka Consulting Group Inc04-Dec-2008
Unveiling the next generation in substrate Technology Amkor Technology, Inc.03-Dec-2008
The Use of the Philips TM1300 for Machine Vis Alacron, Inc.29-Nov-2008
A Practical Guide to Low-Power Design -- User Experience with CPF Power Forward Initiative26-Nov-2008
Parallelization using Polyhedral Analysis ACE Associated Compiler Experts bv25-Nov-2008
The Many Flavors of Low-Power, Low-Cost FPGAs Actel Corporation25-Nov-2008
An Efficient, Interactive Optimization Solution for Analog and RF AWR Corporation10-Nov-2008
AWR VSS 2006 Offers A Comprehensive, Specification-Compliant Solution for WiMAX Systems Design AWR Corporation10-Nov-2008
SPIRAL INDUCTOR MODELING ON RFICs AWR Corporation10-Nov-2008
Advanced Virtual Platform Validation Methodology Jeda Technologies, Inc.06-Nov-2008
Does ESL really need to be that hard to use? Jeda Technologies, Inc.06-Nov-2008
Crosstalk Analysis of a System Based on XAUI HMZd Evaluation Backplane Data SiSoft (Signal Integrity Software, Inc.)24-Sep-2008
Design-for-Variability Teklatech26-Aug-2008
Design of a H.264 Encoder in Five Months Using Application Engine Synthesis Synfora Inc.14-Aug-2008
A Power Integrity Wall Folloes the Power Wall! Anasim® Corp.24-Jul-2008
Record-Breaking - 1 day with PROC Board does more then 256 PCs * 14 days. GIDEL01-May-2008
Features and Implementation of High-Performance 667Mbs and 800Mbs DDRII Memory Systems SiSoft (Signal Integrity Software, Inc.)10-Apr-2008
How to Back Annotate in ORCAD after re-sequencing is done in Allegro Layout. Baykal Technology, Inc.04-Apr-2008
How to transfer Schematics Properties from ORCAD to Allegro Layout Software Baykal Technology, Inc.04-Apr-2008
Counting the Picoseconds: Integrating Timing, Signal and Power Integrity Analysis SiSoft (Signal Integrity Software, Inc.)24-Mar-2008
Demonstration of SerDes Modeling using the Algorithmic Model Interface (AMI) Standard SiSoft (Signal Integrity Software, Inc.)24-Mar-2008
Exploration of Deterministic Jitter Distributions SiSoft (Signal Integrity Software, Inc.)24-Mar-2008
System Level Timing Closure using HSPICE SiSoft (Signal Integrity Software, Inc.)24-Mar-2008
Development Of A Development Of A Real-Time Simulation System Applied Dynamics International19-Mar-2008
Distributed HIL Simulation Applied Dynamics International19-Mar-2008
Predictor Methods in Real-time Simulation Applied Dynamics International19-Mar-2008
Test Automation with the ADvantage Simulation Framework Applied Dynamics International19-Mar-2008
A Low Complexity Method for Detecting Configuration Upset in SRAM Based FPGAs Andraka Consulting Group Inc18-Mar-2008
AN ULTRA-LOW POWER SUBBAND-BASED ELECTRONIC STETHOSCOPE AMI Semiconductor16-Mar-2008
LOW-POWER IMPLEMENTATION OF AN HMM-BASED SOUND ENVIRONMENT CLASSIFICATION ALGORITHM FOR HEARING AID APPLICATION AMI Semiconductor16-Mar-2008
Real-Time Cardiac Arrhythmia Detection Using WOLA Filterbank Analysis of EGM Signals AMI Semiconductor16-Mar-2008
Ultra-Low-Power Application Development with RCore C and Assembler AMI Semiconductor16-Mar-2008
Power Integrity and Energy aware Floor Planning Anasim® Corp.20-Feb-2008
Moving Beyond the Limitations ofSpreadsheets EMA Design Automation01-Feb-2008
A compact Microstrip Stepped-Impedance Resonator and Filter (Microwave Journal) Ansoft LLC16-Jan-2008
A Miniaturized GaAs MMIC Bandpass Filter for the 5 GHz Band (Microwave Journal) Ansoft LLC16-Jan-2008
Protocol Dictates Requirements For RFID ICs (Microwaves & RF) Ansoft LLC16-Jan-2008
View From The Top (Microwave Product Digest) Ansoft LLC16-Jan-2008
Debug Automation Backgrounder SpringSoft, Inc.07-Jan-2008
Visibility Enhancement for Simulation Methodology Backgrounder SpringSoft, Inc.07-Jan-2008
Visibility Enhancement Technology for Simulation SpringSoft, Inc.07-Jan-2008
Interfacing VHDL and Verilog Designs to C++ Models SynaptiCAD, Inc.14-Dec-2007
Adding Video to SOCs: The Diamond 388VDO Video Engine Tensilica08-Oct-2007
Automated Configurable Processor Design Flow (PDF) Tensilica08-Oct-2007
Building a Multi-Issue DSP with Configurable Processor Technology Tensilica08-Oct-2007
Configurable Processors: What, Why, How? Tensilica08-Oct-2007
Developing a High-Performance, Programmable MPEG-4 Decoder by Adding a Programmable SIMD Engine to a Configurable, Extensible Microprocessor Tensilica08-Oct-2007
Diamond Standard Series Architecture White Paper (PDF) Tensilica08-Oct-2007
Flexible VDSL2 Datapath IP for SOC Designs Provides Ready Access to the VDSL2 chip market Tensilica08-Oct-2007
Low-Power, Low-Overhead, High-Fidelity Digital Sound for SOCs: Tensilica’s HiFi 2 Audio Engine Tensilica08-Oct-2007
Processor Core Power Specs: A Cautionary Tale Tensilica08-Oct-2007
Tensilica Xtensa LX Processor with Vectra LX By BDTI Tensilica08-Oct-2007
Why High MHz Does Not Mean High Performance Tensilica08-Oct-2007
XPRES Compiler: Triple-Threat Solution to Code Performance Challenges Tensilica08-Oct-2007
XPRES White Paper: Rapid SOC Development using Automatically Generated Processors Tensilica08-Oct-2007
Xtensa Architecture White Paper (PDF) Tensilica08-Oct-2007
Complex Register Verification Utilizing RVM Based Register Abstraction Layer (RAL) Cypress Semiconductor30-Sep-2007
Avoiding the Pitfalls of Polymorphism Or How to build an Extendable Verification Environment IBM27-Sep-2007
60 GHz Transceiver IC Design Using High-Mobility .15-micron GaAs Process Ansoft LLC30-Aug-2007
Refference Flow For High-Speed Serial Interconnect Design Ansoft LLC30-Aug-2007
RFID Radio Circuit Design in CMOS Ansoft LLC30-Aug-2007
Flash Support for XC166 with XC_Flasher / Usage and Interface of Flash Control DLL (fxc_cntrl.dll) Hewlett Packard18-Aug-2007
Advancement in HPC Improves Engineering and Electronic Cooling Simulations Appro International06-Aug-2007
Altium Corporate Profile (PDF) Altium Limited26-Jun-2007
Altium Designer Feature Set Summary Altium Limited26-Jun-2007
Why Choose Altium Designer Altium Limited26-Jun-2007
Why Partner with Altium Altium Limited26-Jun-2007
Keeping Your Cool in the Data Center while Consolidating and Virtualizing your IT Infrastructure Appro International14-Jun-2007
8051 IP Core Tata Elxsi03-Jun-2007
LIN eVC Tata Elxsi03-Jun-2007
Tata Elxsi Bridge (AHB to APB Bridge) Tata Elxsi03-Jun-2007
Lead-Free Now! Samtec, Inc.02-Jun-2007
Using virtual system prototyping to evaluate VME platforms Mirabilis Design Inc.01-Jun-2007
Z-RAM SHRINKS EMBEDDED MEMORY Innovative Silicon Inc.01-Jun-2007
Accelerating Integration with Verastream Host Integrator Attachmate Corporation.30-May-2007
Attachmate Verastream Host Integrator Architecture and Best Practices Attachmate Corporation.30-May-2007
From Fluid Dynamics to Business Performance Appro International24-May-2007
AN200701-01A On the DC resistance of printed circuit board ground plane. Sysacom R&D plus inc.07-Apr-2007
Characteristic Impedance - A New Definition of Characteristic Impedance Sonnet Software, Inc.05-Apr-2007
Planar Electromagnetic Analysis Sonnet Software, Inc.05-Apr-2007
Planar Electromagnetic Software - Personal Reflections (Microwave Journal: Mar 2005 Cover) Sonnet Software, Inc.05-Apr-2007
21.6: A 3.5 GHz Rotary-Traveling-Wave-Oscillator Clocked Dynamic Logic Family Multigig, Inc.13-Mar-2007
New Generation of EDA Tools Can Significantly Improve Low Power Design Atrenta06-Mar-2007
Architecting, Designing, Implementing, and Verifying Low-Power Digital Integrated Circuits Cadence Design Systems, Inc.20-Feb-2007
Bluespec SystemVerilog for IP Delivery and Effective RTL Debug Bluespec, Inc.14-Feb-2007
Fast Yield-Driven Fracture for Variable Shaped-Beam Mask Writing Blaze DFM, Inc.14-Feb-2007
Lens Aberration-Aware Timing-Driven Placement Blaze DFM, Inc.14-Feb-2007
BVCER – Increased Operating Voltage for SiGe HBTs austriamicrosystems USA, Inc.09-Feb-2007
High Voltage CMOS technologies for robust System-on-Chip design austriamicrosystems USA, Inc.09-Feb-2007
Understanding Integrated Hall Effect Rotary Encoders austriamicrosystems USA, Inc.09-Feb-2007
Drowsy Caches: Simple Techniques for Reducing Leakage Power ARM Inc08-Feb-2007
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation ARM Inc08-Feb-2007
Thread-level Parallelism and Interactive Performance of Desktop Applications ARM Inc08-Feb-2007
Achieving Design Security Requirements using eASIC’s Technology eASIC27-Jan-2007
FlexASIC™ Programmable Array: A solution to the DSM challenge (DesignCon 2005) eASIC27-Jan-2007
How To Implement A Digital Oscilloscope In Structured ASIC Fabric eASIC27-Jan-2007
Routing Density Analysis of Standard Cell vs Standard Metal eASIC27-Jan-2007
Practical Applications of Data Abstraction Techniques for Embedded Systems Debug SpringSoft, Inc.13-Dec-2006
Visibility Enhancement for Silicon Debug SpringSoft, Inc.13-Dec-2006
Transaction-based Debug of PCI Express Embedded SoC Platforms SpringSoft, Inc.12-Dec-2006
System on Chip Prototyping on a FPGA via coreTools and DC FPGA National Semiconductor GmbH18-Nov-2006
A Practical Approach to Process Corner Models of Interconnect RC Extraction National Semiconductor Corporation05-Oct-2006
RTL Coding Technique for Better Coverage Cypress Semiconductors India Private Limited30-Sep-2006
Automatic MilkyWay Technology File Generation Cypress Semiconductor28-Sep-2006
Push Button Flow for Mixed Signal Designs using Recommended Astro™ Script-Based Methodology National Semiconductor Corporation28-Sep-2006
Critical Paths Verification and Debugging with PrimeTime Advanced Features National Semiconductor Corporation26-Sep-2006
The economies of outsourcing Verific Design Automation Inc.31-Aug-2006
EDA story so far... SoftJin Technologies Private Limited21-Aug-2006
A Practical Experience with VCS Native Testbench on a Real World Design National Semiconductor Corporation17-Aug-2006
Mixed-Signal Design and Verification, Static or Dynamic Cypress Semiconductor11-Aug-2006
The Love/Hate Relationship with DDR SDRAM Controllers MOSAID Virtual Silicon19-Jul-2006
Has Your Known Good Die Died? Inapac Technology Inc.18-Jul-2006
A 13 Weeks project in just 1 week, for less then $2K. GIDEL01-May-2006
A Dynamically Reconfigurable Processor for Dataflow Graph Execution. GIDEL01-May-2006
Rapid inductance modeling and netlist reduction boosts RFIC design Edxact24-Apr-2006
A Codeless BIST Processor for Embedded Test and insystem Intellitech02-Mar-2006
A Fast Access Controller for In-System Programming of FLASH Memory Devices Intellitech02-Mar-2006
An Embedded Test and Configuration Processor for Self-Testable and Field Re-Configurable Systems Intellitech02-Mar-2006
Infrastructure IP for Configuration and Test of Boards and Systems Intellitech02-Mar-2006
Infrastructure IP for Programming and Test of in-system Memory Devices Intellitech02-Mar-2006
Novas Verdi Helps Navigate Unfamiliar Territory to Achieve IC Design Harmony: From 1st Hire to 1st Tapeout in 8 Months SpringSoft, Inc.07-Feb-2006
SigmaTel Relies on Verdi Debug System As Critical Element in Verification Strategy SpringSoft, Inc.07-Feb-2006
NET-AN a Full Three Dimensional Parasitic Interconnect Distributed RCL Extractor for Large Full Chip Applications. OEA International, Inc.12-Jan-2006
Optimization of Metal-Metal Comb-Capacitors for RF Applications OEA International, Inc.12-Jan-2006
Spiral and RF-PASS Three Dimensional Design and Analysis Tools for RF Integrated Circuits OEA International, Inc.12-Jan-2006
SILICON DESIGN CHAIN EXTENDS LOW POWER DESIGN COLLABORATION Cadence Design Systems, Inc.09-Jan-2006
Biological Effects of Microwaves: Thermal and Nonthermal Mechanisms* A Report by an Independent Investigator12-Dec-2005
Mobileye Chooses Virage Logic for EyeQ -Game-like interfaces Virage Logic27-Sep-2005
An Alternative Approach to Circuit Design and Assembly for High Speed Interconnections SiliconPipe, Inc.16-Aug-2005
Silicon Design Chain collaboration extends 90-nanometer low-power design into the mainstream Silicon Design Chain16-Aug-2005
Using VN-Spec™ with íManager™ TransEDA14-Apr-2005
Total 219 links listed, not including links in sub-categories.

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