Our 14-day evaluation copy contains your choice of a Redhat or SUSE Linux executable. You will be able to read any mix of Verilog 1995, Verilog 2001, and SystemVerilog files to create a database, attach and configure assertions, and export bind statements and a Verification Plan. You may utilize your own design files or use the examples provided. You may need to download the OVL library from Accellera, or you may utilize the libraries provided by your simulator vendor: IAL from Cadence, QVL from Mentor, or SVA_CG from Synopsys.
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Editorial
Upcoming Events
DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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