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Assertion Based Verification (ABV) has proven to cut debug time in half and has been promoted as the technology having the most impact on reducing verification time and cost. SystemVerilog with ABV has been viewed as the evolving standard for the most complex chip designs. In spite of the promise of ABV, wide scale use has not materialized. Assertion Based Verification is a difficult technology to implement and is perceived as marginally cost effective. If it were easy everyone would have jumped on it by now.
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