Featured Paper by Amre Sultan, Pierre Girodias, Hans van der Schoot
Advanced techniques such as object oriented programming, functional coverage analysis,
and constrained random stimulus generation enable robust, efficient and reusable
testbenches for simulation-based hardware verification. These are the concepts advocated
by the Verification Methodology Manual (VMM) for SystemVerilog. The VMM defines
a comprehensive set of rules, recommendations and guidelines for a verification engineer
to execute the functional verification task more effectively. A corresponding VMM base
class library from Synopsys can be used accordingly as the basis to build VMMcompliant
testbench components, and VMM-based testbenches. However, for the firsttime
user the VMM may appear complicated and even intimidating. It is not necessarily
evident how the VMM principles are to be applied.
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Editorial
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DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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