With design verification taking more and more time of each ASIC project, and with the rate of first silicon success continuing to decline even further, Veritools is now focusing extensively on improving verification productivity with tools that provide a significant advance over what is on the market. These tools are aimed at providing improvements in verification productivity through the use of assertion-based verification with SystemVerilog Assertions.
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Editorial
Upcoming Events
DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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