Viterbi K=7 decoder for UWB (802.15)
K=7 (64 states) G0=171(octal), G1=165(octal), G2=133(octal).
Rate 1/3. Other rates can be supplied by external puncturing.
Silicon proven.
Radix 4 algorithm.
Throughput of 480 Mbit/sec and higher.
Supports partial zero tail bits (only 4 zero tail bits to partial closing of the trellis path).
Parameterizable soft input width.
Parameterizable traceback length (memory depth).
On the fly configurable traceback length, to support low latency.
Zero delay between packets.
Memory type (SRAM / register file), supports Altera/Xilinx coding style for easy synthesis.
Optional controls (decoder_en - for discontinuous data stream, decoder_abort - to reset the decoder).
Supports low power features (clock gating, grey decoding, ...)
Area/Power efficient architecture utilizing RAM for trace back storage.
All-synchronous design using a single clock, except for global asynchronous reset.
Available as verilog source code or as netlist.
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