Title : Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL Company : True Circuits, Inc. Date : 21-Sep-2006 Downloads : 15

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ONE CHALLENGE in designing phase-locked loops (PLLs) for application-specific integrated circuits (ASICs) is providing ample flexibility for a wide variety of applications, including processors and video/chip interfaces. PLLs commonly are used to take low-frequency off-chip clocks, typically from crystals, and generate high-frequency on-chip clocks. The diversity of ASIC applications has also led to diversity in operating frequencies and multiplication factors required from PLLs. For each PLL output frequency and multiplication factor, the loop parameters must be adjusted to minimize jitter and to guarantee stability. There are two jitter parameters of interest. One is long-term jitter, which is the deviation over time in the output clock edge time locations from those of an ideal clock output that is perfectly periodic. The other is period jitter, which is the variation over time in the period of the output clock. For a clock generator PLL, the output clock should track the input clocks as close as possible to minimize long-term jitter. It is also important to minimize the amount of period jitter.

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