Title : Selecting PLLs for ASIC Applications Requires Tradeoffs Company : True Circuits, Inc. Date : 21-Sep-2006 Downloads : 14

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Phase-Locked Loops (PLLs) are commonly used to perform a variety of clock processing tasks, such as clock frequency multiplication and clock deskewing. PLLs, like many other analog IP macros, come with many features and specifications. Selecting the correct PLL early in the design can help the design team make tradeoffs when they are less costly, improve the integration quality of the PLL, and avoid surprises close to tapeout.

A typical PLL application is shown in Figure 1. In this application, a PLL is used to align the setup and hold time window for chip input latches to the input clock edge which is at half the frequency. More specifically, the PLL is used to multiply the clock frequency by two and then align the edges of the distributed output clock to those of the received clock. The PLL accomplishes this task by adjusting the frequency of a voltage-controlled oscillator (VCO) which drives the output clock so that the distributed clock, once divided in half and fed back to the PLL, matches frequency and lines up with the received clock. This simple application requires certain features in the PLL, like the ability to accept a feedback clock and the ability to multiply the input frequency.

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