Title : 2003 IEEE JSSC Paper: Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL Company : True Circuits, Inc. File Name : TCI 2003 JSSC Clock Generator PLL Paper.pdf Size : 587246 Type : application/pdf Date : 09-Apr-2004 Downloads : 200

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A self-biased phase-locked loop (PLL) uses a sampled feedforward filter network and a multistage inverse-linear pro-grammable current mirror for constant loop dynamics that scale with reference frequency and are independent of multiplication factor, output frequency, process, voltage, and temperature. The PLL achieves a multiplication range of 1–4096 with less than 1.7% output jitter. Fabricated in 0.13- m CMOS, the area is 0.182 mm and the supply is 1.5 V.

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