Featured Paper by Ameen Ashraf, Tim Dec, Fing Ch’ng, David Dobrikin, Shoba Srikant
We describe a testbench developed to verify a Single-Instruction Multiple-Data processor. The
testbench is based on OOP methodology and was developed using SystemVerilog TestBench
constructs. We took many concepts from the Reference Verification Methodology recommended
by Synopsys, and incorporated them into our SystemVerilog testbench. The testbench uses
SystemVerilog constraints to generate constrained random stimulus, SystemVerilog covergoups
for functional coverage and a checker that can do DUT/reference model comparisons both on a
per-cycle and per-instruction basis.
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Editorial
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DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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