Featured Paper by Rafy Diaz
Targeting minimum power during netlist creation can lead to oversize area and timing
which might not converge in a strictly area sized design. A technique for margin
selection criteria for synthesizing 90nm blocks with very low dynamic power
requirement is shown. A library selection of high Voltage cells are first used where
proper OCV margins applied leads to a down-sized design during timing-driven layout.
Blocks converge in terms of area and timing constraints afterwards.
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DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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