The choice of hardware-interconnection mechanisms among processor blocks in an SOC affects communication performance and silicon cost. Message-passing software communications have a natural correspondence to data queues, but message passing can be implemented using other types of hardware such as bus-based hardware with global memory. Similarly, the shared-memory software-communications mode has a natural correspondence to bus-based hardware, but shared-memory protocols can be physically implemented even when no globally accessible physical memory exists. This implementation flexibility allows chip designers to implement a spectrum of different task-to-task connections in ways that optimize performance, power, and cost together.
This white paper provides short descriptions of the most common hardware mechanisms—buses, direct connections, and data queues—used to interconnect processor cores on SOCs. Except where explicitly noted, this paper assumes a one-to-one correspondence between tasks and processors. In fact, multiple tasks can be mapped onto one time-sliced processor and tasks can be implemented by other non-programmable hardware blocks.
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Editorial
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DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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