IC designers who work at the deep sub-micron level know that smaller process size means lower per-unit costs, higher performance, and lower power consumption, not an end-run on the laws of physics.
As nets get closer together, parasitic capacitance becomes a design consideration. While designers have long made estimates as to where on the chip these effects might arise between layers, they are turning their attention to lateral effects within layers as they design below .25µm, where nodes become taller, thinner and denser. The best way to manage these effects is to use a parasitic extraction (PX) tool to model them in the design; the worst way is to send a chip to fabrication and have it come back faulty due to unintended influences.
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Editorial
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DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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