Featured Paper by SUDHEER REDDY Y, ERIK N. COMPARINI
Advances in the VLSI technology are making the designs become bigger and more complex. With this, scan methodology is the only option for testability of the designs. Though scan insertion gives most economical solution for silicon validation, it cannot be used if the design has stringent constraints for area, power, extra IO pins and additional DFT effort. In this case we have to depend only on the functional vectors. Despite the fact that functional patterns are not effective for detecting the structural defects, with iterative fault grading process using the fault reports and by targeting the undetected faults with more test data, required fault coverage can be achieved.
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