Featured Paper by David E. Castle, Vijay Gullipalli, Paul McGaugh
In the IBM PowerPC 440 Core, both the setup and access paths of the cache SRAMs are in the critical path; but, depending on timing, one or the other is more critical. It is possible to balance the clock latency to these SRAMs—similar to latch time-borrowing—to minimize the negative slack on both the input and output paths. Choosing the appropriate clock latency for each SRAM is a very important step in this process. In the past, this required a manual trial-and-error process. This paper presents a technique using TCL scripts in the Synopsys® Pilot Design Environment to automatically calculate and balance clock latencies to the SRAMs, from synthesis through place-and-route, for the highest possible performance.
|
Editorial
Upcoming Events
DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
|
|
|
