Featured Paper by Hanif Perwad, Mandar Munishwar
A very important aspect of hybrid/formal verification is the correct generation of input
stimuli using constraints. If the design-under-test is over-constrained, potential bugs
could be hidden during verification. On the other hand, if the design is under-constrained,
the property checkers could flag many false failures, which would greatly increase the
wall-clock time for verifying a design and reaching the required coverage goals. A design
that’s both over-constrained and under-constrained or incorrectly constrained could cause
any or all of the above symptoms.
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