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Featured Paper by Jean JIMENEZ,Emmanuel PLUCHART This paper describes a methodology, developed by STMicroelectronics Set Top Box group, for analyzing the power network integrity of products, which have revealed some failures when tested on board. The analysis takes place after the chip comes back from the fabrication and is based on some reverse-engineering methods. The first part of this paper details the voltage drop measurement conditions on board. It describes the results leading to the assumptions that the power network integrity might have been affected either during fabrication or during the design phase.
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