Featured Paper by Greg Beers, Jamie Kirk, Scott Coates, Cristian Golovanov, Andrew Cirigliano
In advanced technologies at 130nm and finer geometries, the on-chip power integrity has
become a major source of concern. One of the challenges is to identify the resonance frequency
of the RLC circuit formed by the package inductance and the on-chip capacitance. Operating the
chip close to the resonance frequency will result in out-of specification supply voltages and
excessive clock jitter.
|
Editorial
Upcoming Events
DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
|
|
|
