Featured Paper by Joseph Schrand, Ken Umino, Evan Chen
An IC design engineer is often required to perform design related tasks early in the design phase
before all necessary data is present. For example, a designer may be asked to explore power
mesh design and analysis before all IP is procured or RTL is complete. The designer may have
rough targets for die size, maximum power consumption, and maximum IR drop. Rather than
wait, power mesh design and analysis could be started with this early data. This paper covers a
methodology to analyze a power mesh using a dummy netlist consisting of 1000 buffers, and
then proposes a procedure that inserts a power mesh properly aligned with the routing grid.
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Editorial
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