This paper provides a brief discussion of DDR source-synchronous timing concepts and describes five different timing domains. It shows how designers can meet timing budgets for double data rate, single data rate, and cross-domain (clock to strobe) timing domains. Finally, it shows how to improve interconnect timing by reducing crosstalk, inter-symbol interference, reflections and skew, and by controlling simultaneously switching output (SSO) effects.
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Editorial
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DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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