Featured Paper by Scott T. Vento, Ray Yock
With the growth of high level simulation-based verification techniques in recent years, the
quality of IP produced has increased significantly. However, despite this growth there remains a
major hole left by limiting a verification strategy to only simulation. Synopsys Leda HDL coding
style checker and rule specifier is a design and coding guideline checker which fills this void.
Aimed at checking both RTL and gate level code for potential problems with simulating,
synthesizing, testing, and reuse, IBM has found many uses for Leda which has allowed us to find
problems early in the design cycle, and ensure high quality IP release. This paper will examine a
subset of the prepackaged Leda rules which IBM selected and the potential problems averted by
requiring our IP to pass these rules. Additionally the steps taken to fit Leda into IBM’s IP release
methodology will be discussed.
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Editorial
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DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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