Featured Paper by Anand Acharya, Shaun Evans
As designs increase with complexity, the state space in which designs must be verified has
grown to a level that cannot be properly managed using directed methods. A constrained
random approach that leverages RVM offers a method for providing a large amount of valid test
cases that yield a high level of functional coverage.
For designs that perform a type of data transform, system models can be useful collateral for the
verification engineer to leverage. System models are primarily used for system level validation
but can also be used to provide bit accurate expected data for RTL simulations. Integrating
models into a constrained random environment can provide a high level of automation, which in
turn greatly increases the functional coverage and increases the chance of first pass success.
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Editorial
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DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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