Featured Paper by Michael Roeder, Christian Glassner, Wolfgang Hoeld, Fabian Delguste
While several proprietary verification languages have co-existed for many years,
SystemVerilog is the only IEEE approved standard that is supported by all major EDA tool
vendors. Thus, it has the potential to become the unified design and verification language of
the future. SystemVerilog is a sophisticated verification language that supports different
levels of abstractions and creation of layered testbenches. Synopsys methodology
(RVM/VMM) provides a standardized base class library that consists of reusable testbench
components. These components are aimed at boosting reuse and reducing initial testbench
development lead time.
|
Editorial
Upcoming Events
DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
|
|
|
