Featured Paper by Vincent D'Alessandro, Zahi Abuhamdeh, David Chagnon, Kristine Westland, Pam Smoot
It is common knowledge that cost of test is increasing exponentially with the testing
demands of 0.13ì geometries and below. Scan Compression offers the best trade-off potential
for being able to reduce both test time and test volume, the two key components driving test cost.
However, implementation of compression at the top level of a design introduces both test
implementation and routing congestion risks to large complex ASICs that can only be mitigated
at the final phases of development, when the schedule is most critical. Implementation of a
hierarchal compression scheme greatly reduces both test and routing uncertainty.
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Editorial
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DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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