Featured Paper by Alan Carlin, Thanh Nguyen, Tom Powell
Functional verification of pad multiplexing logic has historically been a lengthy and manual
process. Typical SoCs provide tens to hundreds of functional IO, and each IO is expected to
support multiple functional modes in addition to JTAG, scan test modes, and various other test
modes. This can quickly add up to tens of thousands of individual connections to be verified. To
further compound the problem, many of the pad controls are not directly observable in a
traditional simulation, and generating stimulus to uniquely control them can be a daunting
endeavor.
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Editorial
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DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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