Featured Paper by Richard Hayden, Cole O’Berry, John Kuhns
Digital signal processing often requires FFT signal processing. The variables are the
mathematical precision, using either floating point or fixed point computations, and the
number of FFT points required. The design can either be done flat with parallel FFT
butterflies, or serially with a single butterfly, or in some cases a mix between a
completely flat and serial butterfly using more than one butterfly but a subset of total
butterflies. A flat/parallel FFT, utilizes the number of butterflies necessary to do every
point on the design in parallel with a pipelined architecture to meet timing requirements.
Should the amount of hardware for a flat FFT approach prove to be too costly, as in the
case of a large number of FFT points, or greater precision, then an FFT processor and
control sequencer are generally used. This paper and associated scripts answer the need
for automating the RTL creation of a ‘flat’ FFT, and it’s verification. Applications for
this exists in a multitude of DSP applications, including video, radar, and
communications. In this application, Perl is used to generate the FFT RTL, verilog
testbench and modify the Matlab scripts for the specified number of points and bit width.
Perl is also used to create the ‘twiddle factors’ which are passed as verilog parameters to
each FFT butterfly. Matlab is used to create the, input test vectors and verify the correct
operation of the FFT module with the help of VCS
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Editorial
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DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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