Featured Paper by David N. Goldberg
Verification is an essential component of Electronic System Level (ESL) Design. Co-simulation
capabilities help provide higher confidence in the complex transformations performed by ESL
tools. SystemC models and testbenches can play a key role in a smooth transition from systemlevel
modeling and simulation to RTL level simulation.
This case study describes our experience with creating a simulation infrastructure in order to
support SystemC and Verilog RTL co-simulation from the user's perspective and describes the
user experience in integrating system-level models with Verilog simulation using Synopsys'
VCS Verilog RTL simulation solution. Moreover, there were a number of issues and challenges
that are described both from the user's and the developer's perspective.
|
Editorial
Upcoming Events
DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
|
|
|
