TestBencher Pro provides designers with a graphical environment for rapidly generating and testing bus-functional models for VHDL, Verilog, and SystemC. TestBencher generates all of the low-level transaction code, verification code, sequence detection, error reporting and file I/O code allowing you to focus on the design and operation of the model. It accelerates development for both expert and novice users by supporting random data generation, transaction management, and hierarchical models.
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Editorial
Upcoming Events
DAC 2012 at San Francisco CA - Jun 3 - 7, 2012
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