Title : Interfacing VHDL and Verilog Designs to C++ Models Company : SynaptiCAD, Inc. Date : 14-Dec-2007 Downloads : 65

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C++ models add many new capabilities to Verilog and VHDL simulations including the ability to use high-level data structures, constraints, and random data generation. C++ models are also very useful for co-simulation of hardware and software. Despite the advantages of C++ models they have been relegated to simulation of large systems because of the cost associated with setting up the C++ environment. New techniques are now available to automate the process so that C++ models can by used by anybody. Using graphical code generation tools and public domain C++ libraries, engineers can setup a C++ environment and start simulating in just a few hours.

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