Title : Coding Techniques for Bus Functional Models In Verilog, VHDL, and C++ Company : SynaptiCAD, Inc. Date : 14-Dec-2007 Downloads : 210

Rate This File 5 Stars 4 Stars 3 Stars 2 Stars 1 Star

This paper will discuss techniques for creating hierarchical test benches that support re-use at different stages during the design of large-scale systems. A generic test bench architecture will be described that can be implemented using either Verilog, VHDL, or the TestBuilder verification library of SystemC, with notes on techniques required by the quirks of each language. Some of the techniques that will be covered include race avoidance, handling of multiple clock domains, lookup techniques for emulating hierarchical references to BFMs in VHDL, emulation of "class-like" data structures in Verilog and VHDL, and the use of a golden reference model to verify functionality while testing a system against constrained-random data.

---

User Reviews	More Reviews	Review This File
hello i could not access this book - jayanth - Report As Inappropriate
for knowledge - may - Report As Inappropriate